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Additional to the PCie core controller changes added some new PHY changes to help improve and clean up the code. Made lots of silly mistakes, will try to improve in the future. Thanks -Anand Previous changes. v9: https://lore.kernel.org/all/20241016114915.2823-2-linux.amoon@gmail.com/ v8: https://lore.kernel.org/r/20241014135210.224913-2-linux.amoon@gmail.com/ v7: https://lore.kernel.org/all/20241012050611.1908-2-linux.amoon@gmail.com/ v6: https://lore.kernel.org/r/20241006182445.3713-2-linux.amoon@gmail.com/ v5: https://lore.kernel.org/all/20240901183221.240361-2-linux.amoon@gmail.com/ V4: https://lore.kernel.org/all/20240625104039.48311-1-linux.amoon@gmail.com/ V3: https://lore.kernel.org/all/20240622061845.3678-1-linux.amoon@gmail.com/ V2: https://lore.kernel.org/all/20240621064426.282048-1-linux.amoon@gmail.com/ V1: https://lore.kernel.org/all/20240618164133.223194-2-linux.amoon@gmail.com/ Anand Moon (3): PCI: rockchip: Simplify clock handling by using clk_bulk*() function PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature drivers/pci/controller/pcie-rockchip.c | 222 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 35 ++-- 2 files changed, 60 insertions(+), 197 deletions(-) base-commit: 3d5ad2d4eca337e80f38df77de89614aa5aaceb9