From patchwork Tue Nov 26 15:51:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 13886123 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 548B51DDC16; Tue, 26 Nov 2024 15:55:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732636527; cv=none; b=PCQfsiGg+8SoZ8z6F/2scwtx2Wk691+W9JA+RJoPIHcjxu2LI9ffRqPN0z6RXmm3/4djdaRHvTbJDfAr5pl0AzFwtvc+EnSPzOStyjB6p8UFcB/MFG0B/bCx89VzowiSvewHHFAWHIcnTWKX/ANq/awWjRM6wsAfswoeZTz33R8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732636527; c=relaxed/simple; bh=Oo6ywGlbiB40iuvrwv/cQmjt29AdJXkc7lFx/7J3nF8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=XBciNQRFNETtLgubOFZYFXYVTSbPv/ghStxrDaqE+c3yBadgDXI8qlfO4o2S/LK0SUNmRU+1ggRgd2aZq993uisj95KzJ6mDVgDq1/tQvtwwTJNHMpmrzZIW9HDD5TCG5jrq46q8dbhGZQ1c7k4/TEXAXJAElZMKQRtdCpZQLg4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=Uc3ZNNMO; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="Uc3ZNNMO" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AQAk6Hh013064; Tue, 26 Nov 2024 16:54:52 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=selector1; bh=OCFqWclPmUiwBGMA9TvOm8 HW+jw9fUr1fqfQLbTs/3g=; b=Uc3ZNNMOGjnqkvgFgH4+Y3M0wPp0tRezlOzyPh C2aodbCr018B2nroJVqc/r3SSrKVtN+f7s/Hyj+YvoqAWFfM2hcACekQCcgw2sNP Jo7kgdcjurzMWQldJtYKdB/dftyF44I6BN9v8SkDocieUcmzWmIm4dGnfnHYNN6w BF6Iqqa3Pn3P3wxDE159EknrSqkUzbRRvFrP2hmFp9vk+GsAn1y0kcPlqihx+IkB HKif0rCn5F0nFEuDxq3SK8zBi8yDmClzNgI/KtFNLF7JP6fiN+Ygy2Bj8d6VI4rE JmosNWc/o9I2+Wg6DPiL5fQvSgtpVhqFsKF9SLvpbLtdB+Yg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 433tvnk7yr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Nov 2024 16:54:52 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7C84E40045; Tue, 26 Nov 2024 16:53:26 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9469529DE92; Tue, 26 Nov 2024 16:51:36 +0100 (CET) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 26 Nov 2024 16:51:36 +0100 From: Christian Bruel To: , , , , , , , , , , , , CC: , , , , , Christian Bruel Subject: [PATCH v2 0/5] Add STM32MP25 PCIe drivers Date: Tue, 26 Nov 2024 16:51:14 +0100 Message-ID: <20241126155119.1574564-1-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 This patch series adds PCIe drivers STM32MP25 SoC from STMicrolectronics and respective yaml schema for the root complex and device modes. Changes in v2: - Fix st,stm32-pcie-common.yaml dt_binding_check Changes in v1: Address comments from Rob Herring and Bjorn Helgaas: - Drop st,limit-mrrs and st,max-payload-size from this patchset - Remove single reset and clocks binding names and misc yaml cleanups - Split RC/EP common bindings to a separate schema file - Use correct PCIE_T_PERST_CLK_US and PCIE_T_RRS_READY_MS defines - Use .remove instead of .remove_new - Fix bar reset sequence in EP driver - Use cleanup blocks for error handling - Cosmetic fixes Christian Bruel (5): dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings PCI: stm32: Add PCIe host support for STM32MP25 dt-bindings: PCI: Add STM32MP25 PCIe endpoint bindings PCI: stm32: Add PCIe endpoint support for STM32MP25 MAINTAINERS: add entry for ST STM32MP25 PCIe drivers .../bindings/pci/st,stm32-pcie-common.yaml | 45 ++ .../bindings/pci/st,stm32-pcie-ep.yaml | 61 +++ .../bindings/pci/st,stm32-pcie-host.yaml | 99 ++++ MAINTAINERS | 7 + drivers/pci/controller/dwc/Kconfig | 24 + drivers/pci/controller/dwc/Makefile | 2 + drivers/pci/controller/dwc/pcie-stm32-ep.c | 445 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.c | 402 ++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 17 + 9 files changed, 1102 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml create mode 100644 drivers/pci/controller/dwc/pcie-stm32-ep.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h