From patchwork Tue Dec 10 09:33:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13901088 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A3A215779 for ; Tue, 10 Dec 2024 09:34:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733823276; cv=none; b=bz3w6DMKkLXyRn2fuwc5Js330pS7uN3D54y+ROqOuiV0g6aRuXN2rVVxG4FaSiPCU82Opu8ARGxROkdytmNOwQ/Y2m2X11iXM3nkJLzSsuwAvIpFGvgbLY7Ug+dMxLo1M0wIzRIoPhoUbG2dN/kNBEGwIaRRVUCegSxYXRPQAoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733823276; c=relaxed/simple; bh=j1D2I5jgTkzuY1AQu0N7/bHkOdN/fWR3IJJkDC0pa4g=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=F936h0QSmmq8LGHKVyX+Iq991apc3Wr+6UX2mmXAKkFFIEaMFG011ydiTKGMANBLQzi1L9hpIMekUT3Vro9qQAhjhZorHV1ZRsr1lKMJPogUZrcV1j7krCXvHIVkmxN9jYRNVPSIBbMzldyIMvv7051hHFjb+Nd9Pbu6I1RQi4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=liBxbYcu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="liBxbYcu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C979C4CED6; Tue, 10 Dec 2024 09:34:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733823276; bh=j1D2I5jgTkzuY1AQu0N7/bHkOdN/fWR3IJJkDC0pa4g=; h=From:To:Cc:Subject:Date:From; b=liBxbYcuJ8cnLhWIDAP3fkItT5G9fjLqN+r/BgTl7ixSAVJaxk9DjpyJJ/o1R7DYi y6LKisS83nZ0oJ3VHU0ez42OR7PIqTdxRDwzXI+zgm6yWLqBFLY6tPyqduU2HP5PpF 4zDodJOBlNjvFJdvar+ytp3qkTYRNp/w590+D9eiCCI+jjVoR8p3WWDNcAw5s/4L5S sUDUA5bGI6OZ8TVGP48OpbMXxU+jWoirxSZvcfUvumK+0uyCNuQA7XtzWePexUF/uE 6zatcZ1hGcKd5OR+4K5vQv2/vFWlZO8Yz8H3KSgaMRdx9jXpeZPvExRVHTjLszlj/7 vEuh5/wWSC3JA== From: Damien Le Moal To: linux-nvme@lists.infradead.org, Christoph Hellwig , Keith Busch , Sagi Grimberg , linux-pci@vger.kernel.org, Manivannan Sadhasivam , =?utf-8?q?Krzyszt?= =?utf-8?q?of_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Lorenzo Pieralisi Cc: Rick Wertenbroek , Niklas Cassel Subject: [PATCH v3 00/17] NVMe PCI endpoint target driver Date: Tue, 10 Dec 2024 18:33:51 +0900 Message-ID: <20241210093408.105867-1-dlemoal@kernel.org> X-Mailer: git-send-email 2.47.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (Note: follow up to v2 of "NVMe PCI endpoint function driver" patch series). This patch series implements an NVMe target driver for the PCI transport using the PCI endpoint framework. The first 4 patches of this series move and cleanup some nvme code that will be reused in following patches. Patch 5 introduces the PCI transport type to allow setting up ports for the new PCI target controller driver. Patch 6 to 9 are improvements of the target core code to allow creating the PCI controller and processing its nvme commands without the need to rely on fabrics commands like the connect command to create the admin and I/O queues. Patch 10 relaxes the SGL check in nvmet_req_init() to allow for PCI admin commands (which must use PRPs). Patches 11 to 15 improve the set/get feature support of the target code to get closer to achieving NVMe specification compliance. These patches though do not implement support for some mandatory features. Patch 16 is the main patch which introduces the NVMe PCI endpoint target driver. This patch commit message provides and overview of the driver design and operation. Finally, patch 17 documents the NVMe PCI endpoint target driver and provides a user guide explaning how to setup an NVMe PCI endpoint device. The patches are base on Linus 6.13-rc2 tree. This driver has been extensively tested using a Radxa Rock5B board (RK3588 Arm SoC). Some tests have also been done using a Pine Rockpro64 board. However, this board does not support DMA channels for the PCI endpoint controller, leading to very poor performance. Using the Radxa Rock5b board and setting up a 4 queue-pairs controller with a null-blk block device loop target, performance was measured using fio as follows: +----------------------------------+------------------------+ | Workload | IOPS (BW) | +----------------------------------+------------------------+ | Rand read, 4KB, QD=1, 1 job | 14.3k IOPS | | Rand read, 4KB, QD=32, 1 job | 80.8k IOPS | | Rand read, 4KB, QD=32, 4 jobs | 131k IOPS | | Rand read, 128KB, QD=32, 1 job | 16.7k IOPS (2.18 GB/s) | | Rand read, 128KB, QD=32, 4 jobs | 17.4k IOPS (2.27 GB/s) | | Rand read, 512KB, QD=32, 1 job | 5380 IOPS (2.82 GB/s) | | Rand read, 512KB, QD=32, 4 jobs | 5206 IOPS (2.27 GB/s) | | Rand write, 128KB, QD=32, 1 job | 9617 IOPS (1.26 GB/s) | | Rand write, 128KB, QD=32, 4 jobs | 8405 IOPS (1.10 GB/s) | +----------------------------------+------------------------+ These results use the default MDTS of the NVMe enpoint driver of 512 KB. This driver is not intended for production use but rather to be a playground for learning NVMe and exploring/testing new NVMe features while providing reasonably good performance. Changes from v2: - Changed all preparatory patches before patch 16 to move more NVMe generic code out of the PCI endpoint target driver and into the target core. - Changed patch 16 to use directly a target controller instead of a host controller. Many aspects of the command management and DMA transfer management have also been simplified, leading to higher performance. - Change the documentation patch to match the above changes Changes from v1: - Added review tag to patch 1 - Modified patch 4 to: - Add Rick's copyright notice - Improve admin command handling (set_features command) to handle the number of queues feature (among others) to enable Windows host - Improved SQ and CQ work items handling Damien Le Moal (17): nvmet: Add vendor_id and subsys_vendor_id subsystem attributes nvmet: Export nvmet_update_cc() and nvmet_cc_xxx() helpers nvmet: Introduce nvmet_get_cmd_effects_admin() nvmet: Add drvdata field to struct nvmet_ctrl nvme: Add PCI transport type nvmet: Improve nvmet_alloc_ctrl() interface and implementation nvmet: Introduce nvmet_req_transfer_len() nvmet: Introduce nvmet_sq_create() and nvmet_cq_create() nvmet: Add support for I/O queue management admin commands nvmet: Do not require SGL for PCI target controller commands nvmet: Introduce get/set_feature controller operations nvmet: Implement host identifier set feature support nvmet: Implement interrupt coalescing feature support nvmet: Implement interrupt config feature support nvmet: Implement arbitration feature support nvmet: New NVMe PCI endpoint target driver Documentation: Document the NVMe PCI endpoint target driver Documentation/PCI/endpoint/index.rst | 1 + .../PCI/endpoint/pci-nvme-function.rst | 14 + Documentation/nvme/index.rst | 12 + .../nvme/nvme-pci-endpoint-target.rst | 365 +++ Documentation/subsystem-apis.rst | 1 + drivers/nvme/target/Kconfig | 10 + drivers/nvme/target/Makefile | 2 + drivers/nvme/target/admin-cmd.c | 388 ++- drivers/nvme/target/configfs.c | 49 + drivers/nvme/target/core.c | 266 +- drivers/nvme/target/discovery.c | 17 + drivers/nvme/target/fabrics-cmd-auth.c | 14 +- drivers/nvme/target/fabrics-cmd.c | 101 +- drivers/nvme/target/nvmet.h | 110 +- drivers/nvme/target/pci-ep.c | 2627 +++++++++++++++++ include/linux/nvme.h | 2 + 16 files changed, 3858 insertions(+), 121 deletions(-) create mode 100644 Documentation/PCI/endpoint/pci-nvme-function.rst create mode 100644 Documentation/nvme/index.rst create mode 100644 Documentation/nvme/nvme-pci-endpoint-target.rst create mode 100644 drivers/nvme/target/pci-ep.c Reviewed-by: Christoph Hellwig Tested-by: Rick Wertenbroek