From patchwork Wed Jan 22 06:34:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13946907 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05832F9FE; Wed, 22 Jan 2025 06:34:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737527689; cv=none; b=Y5VdeLku7gyw4shBAg9ontt7o8cu10wSMjzqr2TdSX/5n6BEsAL5vyi/xR6VnBLL//QCt9HoRQjFYNxnAwg3ikyHpuIxjhTN9/IuIajR0AD/FY/9c7WLlmwKBh9zS1dnYgCjhTUoo0D99boqhx+7BK3MdNllKvb2FrxIYutud1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737527689; c=relaxed/simple; bh=3DB9otIDmjGh5EklP4A4aNAs/hSS3NxacKHqjEWR630=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=VosWUK5FtpS7d3TK97uLNMA3J30ZCkX1lSKIqKR/F0ciHddqLZNRm6upvjFDiPNzDkeCLO26sl1AfmIIwuLiN4WwR9FY+PGyFAsAaCIZtT0SWHgUiEBGMQHfKChTuDwSJV3KcMZIn0MlN2NJGH7x28uAdbZm55Iz4ASjBLqCqHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Y3/h29DF; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Y3/h29DF" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50M1seb0014528; Wed, 22 Jan 2025 06:34:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=SSQE8uI+/soHl0eCOg2k0i rQMFbAY36Liz7TIMh9kAQ=; b=Y3/h29DF75uv1tRr96c5NZ5QEiUr+hibJnQ5sy jmJLMO/Y4BQSNjwoqEeu9Mldv8dTzWYpv+lRAjCSTmc8J5jGp4gpbmdFWcob9Iai 5CeaqIEuak6iZJFdT7vkpu3xrxAHzLvhlaz1mgF+vCzhi8PPu5JewtJoSOOfLowm w8eg3mzVB3vZGgkg5Ks5c2ZcGcB2Gwx51T7RAKKqDvV6iBfajeL6tb9Gavhyfn6s FdkE2/ymksZVcWzYLYsH/EcFscrQhsj4D+Qo/wMi4mBNSNQBO4YhbPNcqwZm/0od 8TdU0s06RyWHvxV9VT8T2WL0h8SmIn5e8mDs1Tbu/B2yNz/w== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44aqe70jjy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Jan 2025 06:34:31 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50M6YUuB027976 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Jan 2025 06:34:30 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 21 Jan 2025 22:34:24 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 0/7] Add PCIe support for Qualcomm IPQ5332 Date: Wed, 22 Jan 2025 12:04:04 +0530 Message-ID: <20250122063411.3503097-1-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MIYGVZMXeA1JC5NCSENcteaaPLRzJFH0 X-Proofpoint-GUID: MIYGVZMXeA1JC5NCSENcteaaPLRzJFH0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-22_02,2025-01-22_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 spamscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501220046 Patch series adds support for enabling the PCIe controller and UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and PCIe1 is Gen3 X2 are added. This series combines [1] and [2]. [1] introduces IPQ5018 PCIe support and [2] depends on [1] to introduce IPQ5332 PCIe support. Since the community was interested in [2] (please see [3]), tried to revive IPQ5332's PCIe support with v2 of this patch series. v2 of this series pulled in the phy driver from [1] tried to address comments/feedback given in both [1] and [2]. 1. Enable IPQ5018 PCI support (Nitheesh Sekar) - https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ 2. Add PCIe support for Qualcomm IPQ5332 (Praveenkumar I) - https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/ 3. Community interest - https://lore.kernel.org/linux-arm-msm/20240310132915.GE3390@thinkpad/ v7: phy bindings: * Include data type definition to 'num-lanes' controller bindings: * Split the ipq9574 and ipq5332 changes into separate patches dtsi: * Add root port definitions v6: phy bindings: * Fix num-lanes definition phy driver: * Fix num-lanes handling in probe to use generally followed pattern controller bindings: * Give more info in commit log dtsi: * Add assigned-clocks & assigned-clock-rates to controller nodes * Add num-lanes to pcie0_phy v5: phy bindings: * Drop '3x1' & '3x2' from compatible string * Use 'num-lanes' to differentiate instead of '3x1' or '3x2' in compatible string * Describe clocks and resets instead of just maxItems phy driver: * Get num-lanes from DTS * Drop compatible specific init data as there is only one compatible string controller bindings: * Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts dtsi: * Add 'num-lanes' to "pcie1_phy: phy@4b1000" * Make ipq5332 as main and ipq9574 as fallback compatible * Sort controller nodes per address misc: Add R-B tag from Konrad to dts and dtsi patches v4: * phy bindings - Create ipq5332 compatible instead of reusing ipq9574 for bindings * phy bindings - Remove reset-names as the resets are handled with bulk APIs * phy bindings - Fix order in the 'required' section * phy bindings - Remove clock-output-names * dtsi - Add missing reset for pcie1_phy * dtsi - Convert 'reg-names' to a vertical list * dts - Fix nodes sort order * dts - Use property-n followed by property-names v3: * Update the cover letter with the sources of the patches * Rename the dt-bindings yaml file similar to other phys * Drop ipq5332 specific pcie controllor bindings and reuse ipq9574 pcie controller bindings for ipq5332 * Please see patches for specific changes * Set GPL license for phy-qcom-uniphy-pcie-28lp.c v2: Address review comments from V1 Drop the 'required clocks' change that would break ABI (in dt-binding, dts, gcc-ipq5332.c) Include phy driver from the dependent series v1: https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/ Nitheesh Sekar (2): dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy phy: qcom: Introduce PCIe UNIPHY 28LP driver Praveenkumar I (2): arm64: dts: qcom: ipq5332: Add PCIe related nodes arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Varadarajan Narayanan (3): dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574 arm64: dts: qcom: ipq9574: Reorder reg and reg-names dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller .../devicetree/bindings/pci/qcom,pcie.yaml | 15 +- .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 +++++ arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 +++++++++++++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 ++-- drivers/phy/qualcomm/Kconfig | 12 + drivers/phy/qualcomm/Makefile | 1 + .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 286 ++++++++++++++++++ 8 files changed, 763 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc