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Sat, 15 Feb 2025 17:45:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IGk0Wm6pBDN1zI1JP/eN7P464Mszuon80WKDa6iniNlFdMaUXzJp9MDPJ+nFawzsFqmexnMJw== X-Received: by 2002:a17:902:fb45:b0:21f:89e5:2704 with SMTP id d9443c01a7336-221040b1427mr59927565ad.34.1739670333991; Sat, 15 Feb 2025 17:45:33 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220d536455esm49896955ad.74.2025.02.15.17.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Feb 2025 17:45:33 -0800 (PST) From: Krishna Chaitanya Chundru To: andersson@kernel.org, robh@kernel.org, dmitry.baryshkov@linaro.org, manivannan.sadhasivam@linaro.org, krzk@kernel.org, helgaas@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, lpieralisi@kernel.org, kw@linux.com, conor+dt@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree-spec@vger.kernel.org, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru Subject: [PATCH V3 0/2] schemas: pci: bridge: Document PCI L0s & L1 entry delay and N_FTS Date: Sun, 16 Feb 2025 07:15:08 +0530 Message-Id: <20250216014510.3990613-1-krishna.chundru@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7hjcTDzGTUbpgHXunSO7sCN5V3rQpoVW X-Proofpoint-GUID: 7hjcTDzGTUbpgHXunSO7sCN5V3rQpoVW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-15_09,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502160014 Some controllers and endpoints provide provision to program the entry delays of L0s & L1 which will allow the link to enter L0s & L1 more aggressively to save power. Per PCIe r6.0, sec 4.2.5.1, during Link training, a PCIe component captures the N_FTS value it receives. Per 4.2.5.6, when transitioning the Link from L0s to L0, it must transmit N_FTS Fast Training Sequences to enable the receiver to obtain bit and Symbol lock. Components may have device-specific ways to configure N_FTS values to advertise during Link training. Define an n-fts array with an entry for each supported data rate. Signed-off-by: Krishna Chaitanya Chundru --- changes in v3:- - Update the description to specfify about entries of the array (rob) changes in v2:- - Split N_FTS & L1 and L0s entry delay in two patches (bjorn) - Update the commit text, description (bjorn) Krishna Chaitanya Chundru (2): schemas: pci: bridge: Document PCI L0s & L1 entry delay schemas: pci: bridge: Document PCIe N_FTS dtschema/schemas/pci/pci-bus-common.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)