From patchwork Mon Aug 30 08:24:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12464733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0940EC41537 for ; Mon, 30 Aug 2021 08:25:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D898860FF2 for ; Mon, 30 Aug 2021 08:25:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234532AbhH3I0B (ORCPT ); Mon, 30 Aug 2021 04:26:01 -0400 Received: from guitar.tcltek.co.il ([192.115.133.116]:50711 "EHLO mx.tkos.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230216AbhH3I0B (ORCPT ); Mon, 30 Aug 2021 04:26:01 -0400 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id A03B244064E; Mon, 30 Aug 2021 11:24:50 +0300 (IDT) From: Baruch Siach To: Andy Gross , Bjorn Andersson Cc: Baruch Siach , Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 0/3] arm64: IPQ6018 PCIe support Date: Mon, 30 Aug 2021 11:24:49 +0300 Message-Id: X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v3: * Drop applied patches * Rely on generic code for speed setup * Drop unused macros * Formatting fixes Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (1): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Selvam Sathappan Periakaruppan (2): PCI: qcom: add support for IPQ60xx PCIe controller arm64: dts: ipq6018: Add pcie support arch/arm64/boot/dts/qcom/ipq6018.dtsi | 100 +++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 141 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 - 4 files changed, 248 insertions(+), 6 deletions(-)