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If 2kB for cfg0 and 2kB for cfg1 are set, it will make problems when a PCIe card having multiple EPs below a bridge is used. Suggested-by: Pratyush Anand Signed-off-by: Jingoo Han --- Changes since v1: - Fix unintentional modification of I/O size, per Pratyush Anand. arch/arm/boot/dts/exynos5440.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index d600733..94b2cea 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -281,9 +281,9 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00002000 /* configuration space */ + 0x81000000 0 0 0x40002000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40012000 0x40012000 0 0x1ffee000>; /* non-prefetchable memory */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; @@ -302,9 +302,9 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00002000 /* configuration space */ + 0x81000000 0 0 0x60002000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60012000 0x60012000 0 0x1ffee000>; /* non-prefetchable memory */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>;