From patchwork Fri Jun 21 07:25:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 2760671 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9D2B79F472 for ; Fri, 21 Jun 2013 07:26:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BD5A3201E4 for ; Fri, 21 Jun 2013 07:25:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7AC3C201E9 for ; Fri, 21 Jun 2013 07:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030386Ab3FUHZ4 (ORCPT ); Fri, 21 Jun 2013 03:25:56 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:20126 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030336Ab3FUHZy (ORCPT ); Fri, 21 Jun 2013 03:25:54 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOQ000MEFB4P2P0@mailout4.samsung.com>; Fri, 21 Jun 2013 16:25:53 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id D9.4A.29708.00004C15; Fri, 21 Jun 2013 16:25:52 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-5e-51c40000269c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 62.ED.21068.00004C15; Fri, 21 Jun 2013 16:25:52 +0900 (KST) Received: from DOJG1HAN03 ([12.23.120.99]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOQ000N8FB32710@mmp1.samsung.com>; Fri, 21 Jun 2013 16:25:52 +0900 (KST) From: Jingoo Han To: 'Kukjin Kim' , 'Bjorn Helgaas' Cc: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 'Grant Likely' , 'Andrew Murray' , 'Thomas Petazzoni' , 'Thierry Reding' , 'Jason Gunthorpe' , 'Arnd Bergmann' , 'Surendranath Gurivireddy Balla' , 'Siva Reddy Kallam' , 'Thomas Abraham' , 'Tomasz Figa' , 'Pratyush Anand' , 'Mohit KUMAR' , Jingoo Han Subject: [PATCH V10 3/4] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC Date: Fri, 21 Jun 2013 16:25:51 +0900 Message-id: <003c01ce6e50$8f55d890$ae0189b0$@samsung.com> MIME-version: 1.0 Content-type: text/plain; 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Signed-off-by: Jingoo Han Acked-by: Arnd Bergmann --- arch/arm/boot/dts/exynos5440.dtsi | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 03d40c0..1ac4f5b 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -230,4 +230,42 @@ clocks = <&clock 24>; clock-names = "usbhost"; }; + + pcie@290000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + clocks = <&clock 28>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 53>; + }; + + pcie@2a0000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + clocks = <&clock 29>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 56>; + }; };