From patchwork Mon Mar 4 10:23:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 2211971 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 02452DFABD for ; Mon, 4 Mar 2013 10:23:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756259Ab3CDKXs (ORCPT ); Mon, 4 Mar 2013 05:23:48 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:20386 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755776Ab3CDKXr (ORCPT ); Mon, 4 Mar 2013 05:23:47 -0500 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MJ4000V0SU54T30@mailout1.samsung.com>; Mon, 04 Mar 2013 19:23:46 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.48]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 53.5F.02494.13674315; Mon, 04 Mar 2013 19:23:45 +0900 (KST) X-AuditID: cbfee68d-b7f636d0000009be-92-51347631697c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id DB.87.03880.03674315; Mon, 04 Mar 2013 19:23:45 +0900 (KST) Received: from DOJG1HAN02 ([12.23.120.99]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MJ400BESSVKLC90@mmp1.samsung.com>; Mon, 04 Mar 2013 19:23:44 +0900 (KST) From: Jingoo Han To: 'Kukjin Kim' , linux-samsung-soc@vger.kernel.org Cc: linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, 'Surendranath Gurivireddy Balla' , 'Siva Reddy Kallam' , 'Jingoo Han' References: <016b01ce18c2$2c366f10$84a34d30$%han@samsung.com> In-reply-to: <016b01ce18c2$2c366f10$84a34d30$%han@samsung.com> Subject: [PATCH 2/2] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC Date: Mon, 04 Mar 2013 19:23:44 +0900 Message-id: <016c01ce18c2$59bf89d0$0d3e9d70$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac4YwiwG47g5r1j7TCCM6nDu25cMuwAAAxAg Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEIsWRmVeSWpSXmKPExsVy+t8zA13DMpNAg7nTOSzOzjvOZjHj/D4m ByaPz5vkAhijuGxSUnMyy1KL9O0SuDIOrmllKZjOX9Hf2c3YwDiHp4uRk0NCwERib/9xFghb TOLCvfVsILaQwDJGif51cV2MHGA1z+/bdDFyAYUXMUpMefiYEcL5xSixeP0msAY2ATWJL18O s4M0iAh4S6z6Gw9SwyxwnVHi9ZWZzBBDbSUWXe5kB7E5BewkZi7aAbZYWCBEov/eUkYQm0VA VeLP5HWsIDYvUP3xzRNZIGxBiR+T74HZzAJaEut3HmeCsOUlNq95ywxxqLrEo7+6ECcYSUw8 owxRISKx78U7sJMlBNaxS2ydfZIJYpWAxLfJh1ggWmUlNh1ghgSDpMTBFTdYJjBKzEKyeBaS xbOQLJ6FZMUCRpZVjKKpBckFxUnpRYZ6xYm5xaV56XrJ+bmbGCHx1buD8fYB60OMyUDrJzJL iSbnA+MzryTe0NjYxMzE1MTc0tTclDRhJXFeuUsygUIC6YklqdmpqQWpRfFFpTmpxYcYmTg4 pRoYfd7JBartPLArn+35OoZXTDcYXyqKsfqt8dFb/Myz7GnrT6Hf98r/NcWtTtKcb7vJdeUD 9wuqdap23odmGbdOSWALYpZ01T3bbRN04vVPGzaW/8c9I5Lflqk7tMw7+/fgN76A6q8erBXF z6SMVwe3fpnqYbEsk3Hph0OCPzO5fSdGhDBmVpUosRRnJBpqMRcVJwIAf/mmO8UCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAKsWRmVeSWpSXmKPExsVy+t9jAV3DMpNAgx9PGC3OzjvOZjHj/D4m ByaPz5vkAhijGhhtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0tzJUU8hJzU22VXHwC dN0yc4BGKymUJeaUAoUCEouLlfTtME0IDXHTtYBpjND1DQmC6zEyQAMJ6xgzDq5pZSmYzl/R 39nN2MA4h6eLkYNDQsBE4vl9my5GTiBTTOLCvfVsXYxcHEICixglpjx8zAjh/GKUWLx+ExtI FZuAmsSXL4fZQZpFBLwlVv2NB6lhFrjOKPH6ykxmkBohAVuJRZc72UFsTgE7iZmLdrCA2MIC IRL995YygtgsAqoSfyavYwWxeYHqj2+eyAJhC0r8mHwPzGYW0JJYv/M4E4QtL7F5zVtmiKPV JR791YU4wUhi4hlliAoRiX0v3jFOYBSahWTQLCSDZiEZNAtJywJGllWMoqkFyQXFSem5RnrF ibnFpXnpesn5uZsYwfH7THoH46oGi0OMAhyMSjy8Ap+MA4VYE8uKK3MPMUpwMCuJ8EYkmAQK 8aYkVlalFuXHF5XmpBYfYkwG+nMis5Rocj4wteSVxBsam5gZWRqZWRiZmJuTJqwkzst46kmA kEB6YklqdmpqQWoRzBYmDk6pBsaKfjVOJcc0RaH6l54GyyL3GdQel9bN3HvmRtgmf/bvqybO N27N/MCk2Xjh+fsFT3qtn97KCnT2Ti3NNmpYMNP62+U7HJ8vVZw+doD1bvATAS5t6+dzb/JG H6y48G0/R9Xnt7FK3uY7BJMkuRb8fNkjs/DTteD8tOylVUm6S8ynbVd4eeIQ/yElluKMREMt 5qLiRAAWOXRQIwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Exynos5440 has two PCIe controllers which can be used as root complex for PCIe interface. Signed-off-by: Jingoo Han --- arch/arm/boot/dts/exynos5440-ssdk5440.dts | 8 +++++++ arch/arm/boot/dts/exynos5440.dtsi | 32 +++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index 81e2c96..ecf6906 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -43,4 +43,12 @@ rtc { status = "disabled"; }; + + pcie0@40000000 { + reset-gpio = <5>; + }; + + pcie1@60000000 { + reset-gpio = <22>; + }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 0bde96d..16bb994 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -151,4 +151,36 @@ reg = <0x130000 0x1000>; interrupts = <0 17 0>, <0 16 0>; }; + + pcie0@40000000 { + compatible = "samsung,pcie-host"; + reg = <0x40000000 0x4000 + 0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + pcie-host,io_size = <0x4000>; + pcie-host,cfg0_size = <0x100000>; + pcie-host,cfg1_size = <0x100000>; + pcie-host,mem_size = <0x10000000>; + pcie-host,in_mem_size = <0x8000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pcie1@60000000 { + compatible = "samsung,pcie-host"; + reg = <0x60000000 0x4000 + 0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + pcie-host,io_size = <0x4000>; + pcie-host,cfg0_size = <0x100000>; + pcie-host,cfg1_size = <0x100000>; + pcie-host,mem_size = <0x10000000>; + pcie-host,in_mem_size = <0x8000000>; + #address-cells = <1>; + #size-cells = <0>; + }; };