diff mbox

[RFC,2/3] PCI: support PM D0hot->D3 transition reset

Message ID 1239068011-15164-2-git-send-email-yu.zhao@intel.com
State Superseded, archived
Headers show

Commit Message

Yu Zhao April 7, 2009, 1:33 a.m. UTC
PCI PM 1.2 specifies that the device will perform an internal reset upon
transitioning from D3hot to D0 when the NO_SOFT_RESET bit is clear. This
method can be used to reset a function if neither PCIe FLR nor PCI AF FLR
are supported.

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
---
 drivers/pci/pci.c |   34 ++++++++++++++++++++++++++++++++++
 1 files changed, 34 insertions(+), 0 deletions(-)
diff mbox

Patch

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 46ae997..e459a0b 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2085,6 +2085,36 @@  clear:
 	return 0;
 }
 
+static int pci_pm_reset(struct pci_dev *dev, int probe)
+{
+	u16 csr;
+
+	if (!dev->pm_cap)
+		return -ENOTTY;
+
+	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
+	if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
+		return -ENOTTY;
+
+	if (probe)
+		return 0;
+
+	if (dev->current_state != PCI_D0)
+		return -EINVAL;
+
+	csr &= ~PCI_PM_CTRL_STATE_MASK;
+	csr |= PCI_D3hot;
+	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
+	msleep(pci_pm_d3_delay);
+
+	csr &= ~PCI_PM_CTRL_STATE_MASK;
+	csr |= PCI_D0;
+	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
+	msleep(pci_pm_d3_delay);
+
+	return 0;
+}
+
 static int pci_dev_reset(struct pci_dev *dev, int probe)
 {
 	int rc;
@@ -2102,6 +2132,10 @@  static int pci_dev_reset(struct pci_dev *dev, int probe)
 		goto done;
 
 	rc = pci_af_flr(dev, probe);
+	if (rc != -ENOTTY)
+		goto done;
+
+	rc = pci_pm_reset(dev, probe);
 done:
 	up(&dev->dev.sem);