From patchwork Thu May 5 19:33:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 758092 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p45JY14V025963 for ; Thu, 5 May 2011 19:34:02 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754967Ab1EETeA (ORCPT ); Thu, 5 May 2011 15:34:00 -0400 Received: from oproxy2-pub.bluehost.com ([67.222.39.60]:33349 "HELO oproxy2-pub.bluehost.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1754407Ab1EETeA (ORCPT ); Thu, 5 May 2011 15:34:00 -0400 Received: (qmail 7762 invoked by uid 0); 5 May 2011 19:33:58 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy2.bluehost.com with SMTP; 5 May 2011 19:33:58 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=virtuousgeek.org; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:In-Reply-To:References:X-Identified-User; b=LsJJG4uto2ru4sATszS4n2wL4ONS3hw/pCaRUDs/dA4jJjKvZc1tU+KTZG0WoJaph/YVHa0BhjGqPIviJkIDHfcWzvrlzpu7SyLKoab8eD/Ntr/SWSDMh6eDMcqupviW; Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=jbarnes-desktop.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1QI4JC-0001yo-48; Thu, 05 May 2011 13:33:58 -0600 From: Jesse Barnes To: linux-pci@vger.kernel.org Cc: Jesse Barnes Subject: [PATCH 1/3] PCI: add ID-based ordering enable/disable support Date: Thu, 5 May 2011 12:33:48 -0700 Message-Id: <1304624030-1922-2-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1304624030-1922-1-git-send-email-jbarnes@virtuousgeek.org> References: <1304624030-1922-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 05 May 2011 19:34:02 +0000 (UTC) Add support to allow drivers to enable/disable ID-based ordering. Where supported, ID-based ordering can significantly improve the latency of individual requests by preventing them from queueing up behind unrelated traffic. Signed-off-by: Jesse Barnes --- drivers/pci/pci.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 13 +++++++++++ include/linux/pci_regs.h | 2 + 3 files changed, 69 insertions(+), 0 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 44d1c7c..44bf8f0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1834,6 +1834,60 @@ void pci_enable_ari(struct pci_dev *dev) bridge->ari_enabled = 1; } +/** + * pci_enable_ido - enable ID-based ordering on a device + * @dev: the PCI device + * @type: which types of IDO to enable + * + * Enable ID-based ordering on @dev. @type can contain the bits + * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate + * which types of transactions are allowed to be re-ordered. + */ +void pci_enable_ido(struct pci_dev *dev, unsigned long type) +{ + int pos; + u16 ctrl; + + if (!pci_is_pcie(dev)) + return; + + pos = pci_pcie_cap(dev); + if (!pos) + return; + + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); + if (type & PCI_EXP_IDO_REQUEST) + ctrl |= PCI_EXP_IDO_REQ_EN; + if (type & PCI_EXP_IDO_COMPLETION) + ctrl |= PCI_EXP_IDO_CMP_EN; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); +} + +/** + * pci_disable_ido - disable ID-based ordering on a device + * @dev: the PCI device + * @type: which types of IDO to disable + */ +void pci_disable_ido(struct pci_dev *dev, unsigned long type) +{ + int pos; + u16 ctrl; + + if (!pci_is_pcie(dev)) + return; + + pos = pci_pcie_cap(dev); + if (!pos) + return; + + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); + if (type & PCI_EXP_IDO_REQUEST) + ctrl &= ~PCI_EXP_IDO_REQ_EN; + if (type & PCI_EXP_IDO_COMPLETION) + ctrl &= ~PCI_EXP_IDO_CMP_EN; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); +} + static int pci_acs_enable; /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 96f70d7..551ddcb 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -828,6 +828,11 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, return __pci_enable_wake(dev, state, false, enable); } +#define PCI_EXP_IDO_REQUEST (1<<0) +#define PCI_EXP_IDO_COMPLETION (1<<1) +void pci_enable_ido(struct pci_dev *dev, unsigned long type); +void pci_disable_ido(struct pci_dev *dev, unsigned long type); + /* For use by arch with custom probe code */ void set_pcie_port_type(struct pci_dev *pdev); void set_pcie_hotplug_bridge(struct pci_dev *pdev); @@ -1207,6 +1212,14 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, return 0; } +static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) +{ +} + +static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) +{ +} + static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) { return -EIO; diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index be01380..d9acf9b 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -510,6 +510,8 @@ #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ +#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */ +#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */