diff mbox

PCI: Remove MRRS modification from MPS setting code

Message ID 1314923111-20318-1-git-send-email-mason@myri.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jon Mason Sept. 2, 2011, 12:25 a.m. UTC
Modifying the Maximum Read Request Size to 0 (value of 128Bytes) has
massive negative ramifications on some devices.  Without knowing which
devices have this issue, do not modify from the default value when
walking the PCI-E bus.

Signed-off-by: Jon Mason <mason@myri.com>
---
 drivers/pci/probe.c |   36 ------------------------------------
 1 files changed, 0 insertions(+), 36 deletions(-)

Comments

Jesse Barnes Sept. 2, 2011, 12:29 a.m. UTC | #1
On Thu,  1 Sep 2011 19:25:11 -0500
Jon Mason <mason@myri.com> wrote:

> Modifying the Maximum Read Request Size to 0 (value of 128Bytes) has
> massive negative ramifications on some devices.  Without knowing which
> devices have this issue, do not modify from the default value when
> walking the PCI-E bus.
> 
> Signed-off-by: Jon Mason <mason@myri.com>
> ---

Can you collect tested-by lines for this patch as well as add
References: lines for the bug reports?

Thanks,
Jon Mason Sept. 2, 2011, 1:36 p.m. UTC | #2
On Thu, Sep 1, 2011 at 7:29 PM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> On Thu,  1 Sep 2011 19:25:11 -0500
> Jon Mason <mason@myri.com> wrote:
>
>> Modifying the Maximum Read Request Size to 0 (value of 128Bytes) has
>> massive negative ramifications on some devices.  Without knowing which
>> devices have this issue, do not modify from the default value when
>> walking the PCI-E bus.
>>
>> Signed-off-by: Jon Mason <mason@myri.com>
>> ---
>
> Can you collect tested-by lines for this patch as well as add
> References: lines for the bug reports?

It seems to resolve all of the issues reported.  Resending with the
tested-by and References shortly.

Thanks,
Jon

>
> Thanks,
> --
> Jesse Barnes, Intel Open Source Technology Center
>
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diff mbox

Patch

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 8473727..d896c5e 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1394,41 +1394,6 @@  static void pcie_write_mps(struct pci_dev *dev, int mps)
 		dev_err(&dev->dev, "Failed attempting to set the MPS\n");
 }
 
-static void pcie_write_mrrs(struct pci_dev *dev, int mps)
-{
-	int rc, mrrs;
-
-	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
-		int dev_mpss = 128 << dev->pcie_mpss;
-
-		/* For Max performance, the MRRS must be set to the largest
-		 * supported value.  However, it cannot be configured larger
-		 * than the MPS the device or the bus can support.  This assumes
-		 * that the largest MRRS available on the device cannot be
-		 * smaller than the device MPSS.
-		 */
-		mrrs = mps < dev_mpss ? mps : dev_mpss;
-	} else
-		/* In the "safe" case, configure the MRRS for fairness on the
-		 * bus by making all devices have the same size
-		 */
-		mrrs = mps;
-
-
-	/* MRRS is a R/W register.  Invalid values can be written, but a
-	 * subsiquent read will verify if the value is acceptable or not.
-	 * If the MRRS value provided is not acceptable (e.g., too large),
-	 * shrink the value until it is acceptable to the HW.
- 	 */
-	while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
-		rc = pcie_set_readrq(dev, mrrs);
-		if (rc)
-			dev_err(&dev->dev, "Failed attempting to set the MRRS\n");
-
-		mrrs /= 2;
-	}
-}
-
 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
 {
 	int mps = 128 << *(u8 *)data;
@@ -1440,7 +1405,6 @@  static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
 		 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
 
 	pcie_write_mps(dev, mps);
-	pcie_write_mrrs(dev, mps);
 
 	dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
 		 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));