From patchwork Tue Jul 10 15:54:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 1178201 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 6CA10402D2 for ; Tue, 10 Jul 2012 15:58:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756082Ab2GJPzc (ORCPT ); Tue, 10 Jul 2012 11:55:32 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:43454 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752464Ab2GJPz3 (ORCPT ); Tue, 10 Jul 2012 11:55:29 -0400 Received: by mail-pb0-f46.google.com with SMTP id rp8so456687pbb.19 for ; Tue, 10 Jul 2012 08:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references; bh=lfA5YiAYjzcHU22ZhyjGFXCBPs4zjBtbnF0E1fP1ABU=; b=ww/VN0UZ598eIJsDvKxWdtUTutqMIppY5/xoQjuzgJbNmdLWhM5jWzdVTyfqqfYaRC tNZz7PDHyI+J2Uw5fjaA6jWWEWYJd7pw/NJdRK1LmY6f6/S1a71+P2zGBR5D1gJB5219 cV+iRlNl9QQt4jTc5ECvBWD7rx12jmAPXofSQamH46CqVhuJ5aMo7Z6gVNw+cHKLp4YJ DOgKcj7UX711IQVrbSTZyw2o/aVXRdoWBG49pDU92EwSGj2x+aeHXqNZg26uCODvKpBR c9t3Hlx+TpQATGHKf1ZL3W9CrGIrFfKrzBqYWSRHifkf76N8pN3TGificLU4IAZItH0q RLjA== Received: by 10.68.227.163 with SMTP id sb3mr71122479pbc.74.1341935729634; Tue, 10 Jul 2012 08:55:29 -0700 (PDT) Received: from localhost.localdomain ([221.221.21.23]) by mx.google.com with ESMTPS id oq4sm3056662pbb.21.2012.07.10.08.55.21 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 10 Jul 2012 08:55:29 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , Keping Chen , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [RFC PATCH 05/14] PCI: add access functions for PCIe capabilities to hide PCIe spec differences Date: Tue, 10 Jul 2012 23:54:06 +0800 Message-Id: <1341935655-5381-6-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341935655-5381-1-git-send-email-jiang.liu@huawei.com> References: <1341935655-5381-1-git-send-email-jiang.liu@huawei.com> In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Introduce four configuration access functions for PCIe capabilities to hide difference among PCIe Base Spec versions. With these functions, we can remove callers responsible for using pci_pcie_cap_has_*(). pci_pcie_cap_read_word/dword() functions will store the pcie cap register value by passed parameter val,if related pcie cap register is not implemented on the pcie device, the passed parameter val will be set 0 and return -EINVAL. pci_pcie_capability_write_word/dowrd() functions will write the value to pcie cap registers,if related pcie cap register is not implemented on the pcie device, it will return -EINVAL. Signed-off-by: Jiang Liu Signed-off-by: Yijing Wang --- drivers/pci/access.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 10 ++++++ include/linux/pci_regs.h | 19 ++++++++-- 3 files changed, 115 insertions(+), 2 deletions(-) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index ba91a7e..80ae022 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -469,3 +469,91 @@ void pci_cfg_access_unlock(struct pci_dev *dev) raw_spin_unlock_irqrestore(&pci_lock, flags); } EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); + +static int +pci_pcie_cap_get_offset(struct pci_dev *dev, int where, size_t sz) +{ + bool valid; + + if (!pci_is_pcie(dev)) + return -EINVAL; + if (where & (sz - 1)) + return -EINVAL; + + if (where < 0) + valid = false; + else if (where < PCI_EXP_DEVCAP) + valid = true; + else if (where < PCI_EXP_LNKCAP) + valid = pci_pcie_cap_has_devctl(dev); + else if (where < PCI_EXP_SLTCAP) + valid = pci_pcie_cap_has_lnkctl(dev); + else if (where < PCI_EXP_RTCTL) + valid = pci_pcie_cap_has_sltctl(dev); + else if (where < PCI_EXP_DEVCAP2) + valid = pci_pcie_cap_has_rtctl(dev); + else if (where < PCI_EXP_CAP2_SIZE) + valid = pci_pcie_cap_has_cap2(dev); + else + valid = false; + + return valid ? where + pci_pcie_cap(dev) : -EINVAL; +} + +int pci_pcie_cap_read_word(struct pci_dev *dev, int where, u16 *valp) +{ + *valp = 0; + where = pci_pcie_cap_get_offset(dev, where, sizeof(u16)); + if (where >= 0) + return pci_read_config_word(dev, where, valp); + + if (pci_is_pcie(dev) && where == PCI_EXP_SLTSTA && + pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) + *valp = PCI_EXP_SLTSTA_PDS; + + return -EINVAL; +} +EXPORT_SYMBOL(pci_pcie_cap_read_word); + +int pci_pcie_cap_read_dword(struct pci_dev *dev, int where, u32 *valp) +{ + *valp = 0; + where = pci_pcie_cap_get_offset(dev, where, sizeof(u32)); + if (where >= 0) + return pci_read_config_dword(dev, where, valp); + + /* + * Quotation from PCIe Base Spec 3.0: + * For Functions that do not implement the Slot Capabilities, + * Slot Status, and Slot Control registers, these spaces must + * be hardwired to 0b, with the exception of the Presence Detect + * State bit in the Slot Status register of Downstream Ports, + * which must be hardwired to 1b. + */ + if (pci_is_pcie(dev) && where == PCI_EXP_SLTCTL && + pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) + *valp = PCI_EXP_SLTSTA_PDS << 16; + + return -EINVAL; +} +EXPORT_SYMBOL(pci_pcie_cap_read_dword); + +int pci_pcie_cap_write_word(struct pci_dev *dev, int where, u16 val) +{ + where = pci_pcie_cap_get_offset(dev, where, sizeof(u16)); + if (where >= 0) + return pci_write_config_word(dev, where, val); + + return -EINVAL; +} +EXPORT_SYMBOL(pci_pcie_cap_write_word); + +int pci_pcie_cap_write_dword(struct pci_dev *dev, int where, u32 val) +{ + where = pci_pcie_cap_get_offset(dev, where, sizeof(u32)); + if (where >= 0) + return pci_write_config_dword(dev, where, val); + + return -EINVAL; +} +EXPORT_SYMBOL(pci_pcie_cap_write_dword); diff --git a/include/linux/pci.h b/include/linux/pci.h index 346b2d9..78767b2 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1703,6 +1703,11 @@ static inline bool pci_pcie_cap_has_rtctl(const struct pci_dev *pdev) type == PCI_EXP_TYPE_RC_EC; } +extern int pci_pcie_cap_read_word(struct pci_dev *dev, int where, u16 *valp); +extern int pci_pcie_cap_read_dword(struct pci_dev *dev, int where, u32 *valp); +extern int pci_pcie_cap_write_word(struct pci_dev *dev, int where, u16 val); +extern int pci_pcie_cap_write_dword(struct pci_dev *dev, int where, u32 val); + void pci_request_acs(void); bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); bool pci_acs_path_enabled(struct pci_dev *start, @@ -1843,5 +1848,10 @@ static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) */ struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); +int pci_pcie_capability_read_word(struct pci_dev *dev, int where, u16 *val); +int pci_pcie_capability_read_dword(struct pci_dev *dev, int where, u32 *val); +int pci_pcie_capability_write_word(struct pci_dev *dev, int where, u16 val); +int pci_pcie_capability_write_dword(struct pci_dev *dev, int where, u32 val); + #endif /* __KERNEL__ */ #endif /* LINUX_PCI_H */ diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 53274bf..ac60e22 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -542,9 +542,24 @@ #define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ #define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ -#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ +#define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ +#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ +#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ -#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ +#define PCI_EXP_LNKCTL2_TLS 0x0f /* Target Link Speed */ +#define PCI_EXP_LNKCTL2_EC 0x10 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_HASD 0x20 /* Hardware Autonomous Speed Disable */ +#define PCI_EXP_LNKCTL2_SD 0x40 /* Selectable De-emphasis */ +#define PCI_EXP_LNKCTL2_TM 0x380 /* Transmit Margin */ +#define PCI_EXP_LNKCTL2_EMC 0x400 /* Enter Modified Compliance */ +#define PCI_EXP_LNKCTL2_CS 0x800 /* Compliance SOS */ +#define PCI_EXP_LNKCTL2_CD 0x1000 /* Compliance De-emphasis */ +#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ +#define PCI_EXP_LNKSTA2_CDL 0x01 /* Current De-emphasis Level */ +#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ +#define PCI_EXP_SLTCTL2 56 /* Slot Control 2*/ +#define PCI_EXP_SLTSTA2 58 /* Slot Status 2*/ +#define PCI_EXP_CAP2_SIZE 60 /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)