From patchwork Wed Aug 1 15:54:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 1265101 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id E62DBDF215 for ; Wed, 1 Aug 2012 16:01:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756110Ab2HAQAR (ORCPT ); Wed, 1 Aug 2012 12:00:17 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:59609 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756099Ab2HAQAM (ORCPT ); Wed, 1 Aug 2012 12:00:12 -0400 Received: by pbbrp8 with SMTP id rp8so1288525pbb.19 for ; Wed, 01 Aug 2012 09:00:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=9KbgfFafN4JEPYLM3hcbK49R4MpURhSPHnyum6gWJ2o=; b=JC8IC2eTKkpn1aH4WYNxCK6R3v90i1fQoE2YQIQiqdoCL8VE1qWncZciyCK4HB5zy3 gcM9zQX6ybCcPxNOomAJ/L28+8PQ0+SURsWJ/3/u0zJMpNKLmATINZhOxcgCFs8dJNdg nnXybeohoWhIADbmr0+vl8AxN9Pc2SEP2D2hX65bHY6tggRCiz1aEwBcV1bIx14qh/h8 KWbuPgypTjS72p0/fTdC7PzmQHbgnUC4LkQ1470ybQndeCA3Jo8HIQlh8TOce9ZugIGD jbvfEfE94skzg+382AYiqxeqHcg3ThxT7wGW9kI1Otsdy2qbnmCb0cETwlmVVVBE3eAq LRjg== Received: by 10.68.201.195 with SMTP id kc3mr53702448pbc.33.1343836812079; Wed, 01 Aug 2012 09:00:12 -0700 (PDT) Received: from localhost.localdomain ([58.250.81.2]) by mx.google.com with ESMTPS id pe8sm2816231pbc.76.2012.08.01.09.00.02 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 01 Aug 2012 09:00:10 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile , Matt Porter , Alexandre Bounine Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [PATCH v3 30/32] PCI/tsi721: use PCIe capabilities access functions to simplify implementation Date: Wed, 1 Aug 2012 23:54:35 +0800 Message-Id: <1343836477-7287-31-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify tsi721 driver's implementation. Signed-off-by: Jiang Liu Acked-by: Alexandre Bounine --- drivers/rapidio/devices/tsi721.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c index 722246c..5970c43 100644 --- a/drivers/rapidio/devices/tsi721.c +++ b/drivers/rapidio/devices/tsi721.c @@ -2212,9 +2212,8 @@ static int __devinit tsi721_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct tsi721_device *priv; - int i, cap; + int i; int err; - u32 regval; priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL); if (priv == NULL) { @@ -2320,20 +2319,16 @@ static int __devinit tsi721_probe(struct pci_dev *pdev, dev_info(&pdev->dev, "Unable to set consistent DMA mask\n"); } - cap = pci_pcie_cap(pdev); - BUG_ON(cap == 0); + BUG_ON(!pci_is_pcie(pdev)); /* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */ - pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, ®val); - regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN | - PCI_EXP_DEVCTL_NOSNOOP_EN); - regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT; - pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval); + pci_pcie_capability_change_dword(pdev, PCI_EXP_DEVCTL, + 0x2 << MAX_READ_REQUEST_SZ_SHIFT, + PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN | + PCI_EXP_DEVCTL_NOSNOOP_EN); /* Adjust PCIe completion timeout. */ - pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, ®val); - regval &= ~(0x0f); - pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2); + pci_pcie_capability_change_dword(pdev, PCI_EXP_DEVCTL2, 0x2, 0xf); /* * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block