From patchwork Wed Mar 13 23:28:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 2266591 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 89C45DF215 for ; Wed, 13 Mar 2013 23:32:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964954Ab3CMXcK (ORCPT ); Wed, 13 Mar 2013 19:32:10 -0400 Received: from aserp1040.oracle.com ([141.146.126.69]:51230 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964922Ab3CMX2l (ORCPT ); Wed, 13 Mar 2013 19:28:41 -0400 Received: from acsinet21.oracle.com (acsinet21.oracle.com [141.146.126.237]) by aserp1040.oracle.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.1) with ESMTP id r2DNSacN026673 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 13 Mar 2013 23:28:36 GMT Received: from acsmt358.oracle.com (acsmt358.oracle.com [141.146.40.158]) by acsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id r2DNSZRe007060 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 13 Mar 2013 23:28:36 GMT Received: from abhmt103.oracle.com (abhmt103.oracle.com [141.146.116.55]) by acsmt358.oracle.com (8.12.11.20060308/8.12.11) with ESMTP id r2DNSZQA026138; Wed, 13 Mar 2013 18:28:35 -0500 Received: from linux-siqj.site (/10.132.126.191) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 13 Mar 2013 16:28:35 -0700 From: Yinghai Lu To: Bjorn Helgaas , Ram Pai Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yinghai Lu Subject: [PATCH v3 25/27] PCI: Make piix4 quirk to use addon_res Date: Wed, 13 Mar 2013 16:28:20 -0700 Message-Id: <1363217302-14383-26-git-send-email-yinghai@kernel.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1363217302-14383-1-git-send-email-yinghai@kernel.org> References: <1363217302-14383-1-git-send-email-yinghai@kernel.org> X-Source-IP: acsinet21.oracle.com [141.146.126.237] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org After they are put in add-on resources, they will be safely claimed later. Signed-off-by: Yinghai Lu --- drivers/pci/quirks.c | 93 +++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 77 insertions(+), 16 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 0369fb6..7e5392c 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -383,14 +383,14 @@ static void quirk_ali7101_acpi(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); -static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) +static int piix4_read_io(struct pci_dev *dev, struct resource *res, int port) { u32 devres; u32 mask, size, base; + struct pci_bus_region bus_region; pci_read_config_dword(dev, port, &devres); - if ((devres & enable) != enable) - return; + mask = (devres >> 16) & 15; base = devres & 0xffff; size = 16; @@ -400,23 +400,53 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p break; size = bit; } - /* - * For now we only print it out. Eventually we'll want to - * reserve it (at least if it's in the 0x1000+ range), but - * let's get enough confirmation reports first. - */ base &= -size; - dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); + + bus_region.start = base; + bus_region.end = base + size - 1; + res->flags |= IORESOURCE_IO; + pcibios_bus_to_resource(dev, res, &bus_region); + dev_info(&dev->dev, "PIO at %pR\n", res); + + return 0; } +static int piix4_write_io(struct pci_dev *dev, struct resource *res, int port) +{ + u32 devres; + struct pci_bus_region bus_region; + + pcibios_resource_to_bus(dev, &bus_region, res); -static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) + pci_read_config_dword(dev, port, &devres); + devres &= 0xffff0000; + devres |= bus_region.start & 0xffff; + pci_write_config_dword(dev, port, devres); + + return 0; +} +static struct resource_ops piix4_io_ops = { + .read = piix4_read_io, + .write = piix4_write_io, +}; +static void piix4_io_quirk(struct pci_dev *dev, char *name, unsigned int port, + unsigned int enable) { u32 devres; - u32 mask, size, base; pci_read_config_dword(dev, port, &devres); if ((devres & enable) != enable) return; + + pci_add_dev_addon_resource(dev, port, 0, &piix4_io_ops, name); +} + +static int piix4_read_mem(struct pci_dev *dev, struct resource *res, int port) +{ + u32 devres; + u32 mask, size, base; + struct pci_bus_region bus_region; + + pci_read_config_dword(dev, port, &devres); base = devres & 0xffff0000; mask = (devres & 0x3f) << 16; size = 128 << 16; @@ -426,12 +456,43 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int break; size = bit; } - /* - * For now we only print it out. Eventually we'll want to - * reserve it, but let's get enough confirmation reports first. - */ base &= -size; - dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); + bus_region.start = base; + bus_region.end = base + size - 1; + res->flags |= IORESOURCE_MEM; + pcibios_bus_to_resource(dev, res, &bus_region); + dev_info(&dev->dev, "MMIO at %pR\n", res); + + return 0; +} +static int piix4_write_mem(struct pci_dev *dev, struct resource *res, int port) +{ + u32 devres; + struct pci_bus_region bus_region; + + pcibios_resource_to_bus(dev, &bus_region, res); + + pci_read_config_dword(dev, port, &devres); + devres &= 0x0000ffff; + devres |= bus_region.start & 0xffff0000; + pci_write_config_dword(dev, port, devres); + + return 0; +} +static struct resource_ops piix4_mem_ops = { + .read = piix4_read_mem, + .write = piix4_write_mem, +}; +static void piix4_mem_quirk(struct pci_dev *dev, char *name, unsigned int port, + unsigned int enable) +{ + u32 devres; + + pci_read_config_dword(dev, port, &devres); + if ((devres & enable) != enable) + return; + + pci_add_dev_addon_resource(dev, port, 0, &piix4_mem_ops, name); } /*