From patchwork Wed May 22 13:12:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 2601831 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id AC0E440077 for ; Wed, 22 May 2013 13:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754320Ab3EVNMs (ORCPT ); Wed, 22 May 2013 09:12:48 -0400 Received: from mail.free-electrons.com ([94.23.35.102]:38818 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752705Ab3EVNMr (ORCPT ); Wed, 22 May 2013 09:12:47 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id A66C7E43; Wed, 22 May 2013 15:12:46 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1AF5F7C4; Wed, 22 May 2013 15:12:46 +0200 (CEST) From: Thomas Petazzoni To: Bjorn Helgaas , linux-pci@vger.kernel.org, Jason Cooper , Andrew Lunn , Gregory Clement Cc: Ezequiel Garcia , Lior Amsalem , Maen Suleiman , Jason Gunthorpe , linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/4] pci: mvebu: fix the emulation of the status register Date: Wed, 22 May 2013 15:12:38 +0200 Message-Id: <1369228358-32580-5-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1369228358-32580-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In a PCI configuration header, the 'devsel' bits of the status register are read-only, and indicate the timing of the secondary interface. Currently, we implement them as read/write, so when the Linux PCI core writes all 1's to this register, it gets 11b as the 'devsel' value, which is reserved. This commit fixes the PCI-to-PCI bridge emulation of the Marvell PCIe driver to ensure those bits remain set to 00b, which indicate a fast devsel decoding. This allows to fix the lspci -v output from: Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0 to: Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0 Signed-off-by: Thomas Petazzoni --- drivers/pci/host/pci-mvebu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index c887598..d730bf4 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -490,6 +490,11 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, case PCI_COMMAND: bridge->command = value & 0xffff; bridge->status = value >> 16; + /* + * The devsel bits are read-only, and we want to keep + * them set to 0 + */ + bridge->status &= ~PCI_STATUS_DEVSEL_MASK; break; case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: