From patchwork Sat Aug 24 15:47:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aravind Gopalakrishnan X-Patchwork-Id: 2849242 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BB065BF546 for ; Sat, 24 Aug 2013 15:49:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8386420268 for ; Sat, 24 Aug 2013 15:49:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C58720177 for ; Sat, 24 Aug 2013 15:49:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754675Ab3HXPtQ (ORCPT ); Sat, 24 Aug 2013 11:49:16 -0400 Received: from [213.199.154.189] ([213.199.154.189]:35111 "EHLO db8outboundpool.messaging.microsoft.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1754662Ab3HXPtP (ORCPT ); Sat, 24 Aug 2013 11:49:15 -0400 Received: from mail207-db8-R.bigfish.com (10.174.8.251) by DB8EHSOBE017.bigfish.com (10.174.4.80) with Microsoft SMTP Server id 14.1.225.22; Sat, 24 Aug 2013 15:48:04 +0000 Received: from mail207-db8 (localhost [127.0.0.1]) by mail207-db8-R.bigfish.com (Postfix) with ESMTP id 5BCA24C03DD; Sat, 24 Aug 2013 15:48:04 +0000 (UTC) X-Forefront-Antispam-Report: CIP:165.204.84.221; KIP:(null); UIP:(null); IPV:NLI; H:atltwp01.amd.com; RD:none; EFVD:NLI X-SpamScore: 12 X-BigFish: VPS12(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hz70kd2iz1de098h177df4h17326ah186068h8275eh8275bh1de097h3284oa1495iz2dh839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h1155h) Received: from mail207-db8 (localhost.localdomain [127.0.0.1]) by mail207-db8 (MessageSwitch) id 1377359279481092_6222; Sat, 24 Aug 2013 15:47:59 +0000 (UTC) Received: from DB8EHSMHS030.bigfish.com (unknown [10.174.8.232]) by mail207-db8.bigfish.com (Postfix) with ESMTP id 69D8D1E0031; Sat, 24 Aug 2013 15:47:59 +0000 (UTC) Received: from atltwp01.amd.com (165.204.84.221) by DB8EHSMHS030.bigfish.com (10.174.4.40) with Microsoft SMTP Server id 14.16.227.3; Sat, 24 Aug 2013 15:47:58 +0000 X-WSS-ID: 0MS1L35-07-C67-02 X-M-MSG: Received: from satlvexedge01.amd.com (satlvexedge01.amd.com [10.177.96.28]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.2.1) with ESMTPS id 2CD0ECAE799; Sat, 24 Aug 2013 10:45:04 -0500 (CDT) Received: from SATLEXDAG02.amd.com (10.181.40.5) by satlvexedge01.amd.com (10.177.96.28) with Microsoft SMTP Server (TLS) id 14.2.328.9; Sat, 24 Aug 2013 10:47:59 -0500 Received: from SAUSEXDAG06.amd.com (163.181.55.7) by SATLEXDAG02.amd.com (10.181.40.5) with Microsoft SMTP Server (TLS) id 14.2.328.9; Sat, 24 Aug 2013 11:47:55 -0400 Received: from sos-lamar0.amd.com (163.181.55.254) by sausexdag06.amd.com (163.181.55.7) with Microsoft SMTP Server id 14.2.328.9; Sat, 24 Aug 2013 10:47:54 -0500 From: Aravind Gopalakrishnan To: , , , , , , , , , CC: Aravind Gopalakrishnan Subject: [PATCH 1/1 V2] AMD64_EDAC: Fix incorrect wrap arounds due to left shift beyond 32 bits. Date: Sat, 24 Aug 2013 10:47:48 -0500 Message-ID: <1377359268-3435-1-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 X-OriginatorOrg: amd.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Link to the bug report: http://marc.info/?l=linux-edac&m=137692201732220&w=2 dct_base and dct_limit obtain 32 bit register values when they read their respective pci config space registers. A left shift beyond 32 bits will cause them to wrap around. Similar case for chan_addr as can be seen from the bug report. In the patch, we rectify this by casting chan_addr to u64 and by comparing dct_base and dct_limit against (sys_addr >> 27) Change from V1: - Fix chan_offset to use left-shifted version of dct_base. Signed-off-by: Aravind Gopalakrishnan diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b86228c..64cfcaf 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1558,11 +1558,12 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, } /* Verify sys_addr is within DCT Range. */ - dct_base = (dct_sel_baseaddr(pvt) << 27); - dct_limit = (((dct_cont_limit_reg >> 11) & 0x1FFF) << 27) | 0x7FFFFFF; + dct_base = (u64) dct_sel_baseaddr(pvt); + dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF; if (!(dct_cont_base_reg & BIT(0)) && - !(dct_base <= sys_addr && dct_limit >= sys_addr)) + !(dct_base <= (sys_addr >> 27) && + dct_limit >= (sys_addr >> 27))) return -EINVAL; /* Verify number of dct's that participate in channel interleaving. */ @@ -1584,7 +1585,7 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, if (leg_mmio_hole && (sys_addr >= BIT_64(32))) chan_offset = dhar_offset; else - chan_offset = dct_base; + chan_offset = dct_base << 27; chan_addr = sys_addr - chan_offset; @@ -1614,7 +1615,7 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, amd64_read_pci_cfg(pvt->F1, DRAM_CONT_HIGH_OFF + (int) channel * 4, &tmp); - chan_addr += ((tmp >> 11) & 0xfff) << 27; + chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27; } f15h_select_dct(pvt, channel);