From patchwork Mon Sep 9 13:13:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 2860761 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 17E649F2D6 for ; Mon, 9 Sep 2013 13:18:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F35F020462 for ; Mon, 9 Sep 2013 13:18:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C01FB20480 for ; Mon, 9 Sep 2013 13:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752610Ab3IINSR (ORCPT ); Mon, 9 Sep 2013 09:18:17 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:19153 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751969Ab3IINRJ (ORCPT ); Mon, 9 Sep 2013 09:17:09 -0400 Received: from 172.24.2.119 (EHLO szxeml207-edg.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.2a-FCS FastPath queued) with ESMTP id ADZ88469; Mon, 09 Sep 2013 21:13:33 +0800 (CST) Received: from SZXEML423-HUB.china.huawei.com (10.82.67.162) by szxeml207-edg.china.huawei.com (172.24.2.56) with Microsoft SMTP Server (TLS) id 14.1.323.7; Mon, 9 Sep 2013 21:13:31 +0800 Received: from localhost (10.135.76.69) by szxeml423-hub.china.huawei.com (10.82.67.162) with Microsoft SMTP Server id 14.1.323.7; Mon, 9 Sep 2013 21:13:25 +0800 From: Yijing Wang To: Bjorn Helgaas , Chris Metcalf , Greg Kroah-Hartman , David Airlie , Mike Marciniszyn , Roland Dreier , Roland Dreier CC: , Mark Einon , Sean Hefty , Hal Rosenstock , , , Yijing Wang , Hanjun Guo Subject: [PATCH 6/6] radeon: Use pcie_get_readrq() and pcie_set_readrq() to simplify code Date: Mon, 9 Sep 2013 21:13:08 +0800 Message-ID: <1378732388-4508-7-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.11.msysgit.1 In-Reply-To: <1378732388-4508-1-git-send-email-wangyijing@huawei.com> References: <1378732388-4508-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.135.76.69] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use pcie_get_readrq() and pcie_set_readrq() functions to simplify code. Signed-off-by: Yijing Wang Reviewed-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreen.c | 19 ++++++------------- 1 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index d5b49e3..b191f92 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1169,23 +1169,16 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) { - u16 ctl, v; - int err; - - err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl); - if (err) - return; - - v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12; + int readrq; + u16 v; + readrq = pcie_get_readrq(rdev->pdev); + v = ffs(readrq) - 8; /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it * to avoid hangs or perfomance issues */ - if ((v == 0) || (v == 6) || (v == 7)) { - ctl &= ~PCI_EXP_DEVCTL_READRQ; - ctl |= (2 << 12); - pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl); - } + if ((v == 0) || (v == 6) || (v == 7)) + pcie_set_readrq(rdev->pdev, 512); } static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)