From patchwork Thu Oct 31 23:32:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 3122661 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 75E829F3E3 for ; Thu, 31 Oct 2013 23:27:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 59EFA20451 for ; Thu, 31 Oct 2013 23:33:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7B61620411 for ; Thu, 31 Oct 2013 23:33:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753534Ab3JaXdF (ORCPT ); Thu, 31 Oct 2013 19:33:05 -0400 Received: from quartz.orcorp.ca ([184.70.90.242]:55294 "EHLO quartz.orcorp.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752607Ab3JaXdE (ORCPT ); Thu, 31 Oct 2013 19:33:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=obsidianresearch.com; s=rsa1; h=Message-Id:Date:Subject:Cc:To:From; bh=vbNzk+06VLclmKllP1OB84RAr0JGBdWueXamS2O208k=; b=wyESDWAvkVvzDP8fQH5zvedYebtHYT2yJKP80U3X2T1dVHqJRgZsQIOLbNRuP9Qb+Wn/SZu7iCH2UEe4e323t912/KtrHCjiM78qlcObg7OD4yDkr8TuS9XQlQZmG6s5N3MaPUJpVAm0gpJOe+Wx8kybFtMx4GPlMQNaUeuIcRI=; Received: from [10.0.0.161] (helo=jggl.edm.orcorp.ca) by quartz.orcorp.ca with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Vc1jZ-0002sp-Vl; Thu, 31 Oct 2013 17:33:01 -0600 From: Jason Gunthorpe To: Thomas Petazzoni Cc: Bjorn Helgaas , Jason Cooper , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org Subject: [PATCH 1/2] PCI: mvebu - The bridge should obey the MEM and IO command bits Date: Thu, 31 Oct 2013 17:32:59 -0600 Message-Id: <1383262380-6984-1-git-send-email-jgunthorpe@obsidianresearch.com> X-Mailer: git-send-email 1.8.1.2 X-Broken-Reverse-DNS: no host name found for IP address 10.0.0.161 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When PCI_COMMAND_MEMORY/PCI_COMMAND_IO are cleared the bridge should not allocate windows or even look at the window limit/base registers. Otherwise it can attempt to setup bogus windows that the PCI core code creates during discovery. The core will leave PCI_COMMAND_IO cleared if it doesn't need an IO window. Have mvebu_pcie_handle_*_change respect the bits, and call the change function whenever the bits changes. Signed-off-by: Jason Gunthorpe Tested-by: Thomas Petazzoni --- drivers/pci/host/pci-mvebu.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index 19d77c9..721fca9 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -279,7 +279,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) /* Are the new iobase/iolimit values invalid? */ if (port->bridge.iolimit < port->bridge.iobase || - port->bridge.iolimitupper < port->bridge.iobaseupper) { + port->bridge.iolimitupper < port->bridge.iobaseupper || + !(port->bridge.command & PCI_COMMAND_IO)) { /* If a window was configured, remove it */ if (port->iowin_base) { @@ -316,7 +317,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) { /* Are the new membase/memlimit values invalid? */ - if (port->bridge.memlimit < port->bridge.membase) { + if (port->bridge.memlimit < port->bridge.membase || + !(port->bridge.command & PCI_COMMAND_MEMORY)) { /* If a window was configured, remove it */ if (port->memwin_base) { @@ -464,8 +466,16 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, switch (where & ~3) { case PCI_COMMAND: + { + u32 old = bridge->command; + bridge->command = value & 0xffff; + if ((old ^ bridge->command) & PCI_COMMAND_IO) + mvebu_pcie_handle_iobase_change(port); + if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) + mvebu_pcie_handle_membase_change(port); break; + } case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;