From patchwork Tue Nov 26 18:02:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 3240071 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 011CA9F3A0 for ; Tue, 26 Nov 2013 18:03:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BFAF320445 for ; Tue, 26 Nov 2013 18:03:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7EF3D20444 for ; Tue, 26 Nov 2013 18:03:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752200Ab3KZSDF (ORCPT ); Tue, 26 Nov 2013 13:03:05 -0500 Received: from quartz.orcorp.ca ([184.70.90.242]:50776 "EHLO quartz.orcorp.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753538Ab3KZSDE (ORCPT ); Tue, 26 Nov 2013 13:03:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=obsidianresearch.com; s=rsa1; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=7R/iwvAHwF0Jot8LynoFRegedn4GMrsRkn09XEWQXTE=; b=cLo2LdNC9f09Lc3RSbXQXiqwrXTt57x9Hba+X/rSejeXzBBjp2ADk9wc/+9NjASpgUklL5h2/dRsVbAQQ6jY5ocXpDJFQzZmRPqwKKq/QNVO6Et+AwnKu4oj7jPa/3/ZFDAUMCVA4OcIgRXAWrSzIoRrczG7EHxwkd1uTLYNEtI=; Received: from [10.0.0.161] (helo=jggl.edm.orcorp.ca) by quartz.orcorp.ca with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1VlMyP-0001j3-J2; Tue, 26 Nov 2013 11:02:57 -0700 From: Jason Gunthorpe To: Bjorn Helgaas , Jason Cooper , Thomas Petazzoni Cc: Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org Subject: [PATCH RESEND v3 1/2] PCI: mvebu - The bridge should obey the MEM and IO command bits Date: Tue, 26 Nov 2013 11:02:54 -0700 Message-Id: <1385488975-27694-3-git-send-email-jgunthorpe@obsidianresearch.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1385488975-27694-1-git-send-email-jgunthorpe@obsidianresearch.com> References: <1385488975-27694-1-git-send-email-jgunthorpe@obsidianresearch.com> X-Broken-Reverse-DNS: no host name found for IP address 10.0.0.161 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When PCI_COMMAND_MEMORY/PCI_COMMAND_IO are cleared the bridge should not allocate windows or even look at the window limit/base registers. Otherwise it can attempt to setup bogus windows that the PCI core code creates during discovery. The core will leave PCI_COMMAND_IO cleared if it doesn't need an IO window. Have mvebu_pcie_handle_*_change respect the bits, and call the change function whenever the bits changes. Signed-off-by: Jason Gunthorpe Tested-by: Thomas Petazzoni --- drivers/pci/host/pci-mvebu.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) Bjorn, this is now ready to go for the next merge window. Can you take it through your tree? Thanks diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index 327ee2f..6fde82b 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -300,7 +300,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) /* Are the new iobase/iolimit values invalid? */ if (port->bridge.iolimit < port->bridge.iobase || - port->bridge.iolimitupper < port->bridge.iobaseupper) { + port->bridge.iolimitupper < port->bridge.iobaseupper || + !(port->bridge.command & PCI_COMMAND_IO)) { /* If a window was configured, remove it */ if (port->iowin_base) { @@ -337,7 +338,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) { /* Are the new membase/memlimit values invalid? */ - if (port->bridge.memlimit < port->bridge.membase) { + if (port->bridge.memlimit < port->bridge.membase || + !(port->bridge.command & PCI_COMMAND_MEMORY)) { /* If a window was configured, remove it */ if (port->memwin_base) { @@ -490,8 +492,16 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, switch (where & ~3) { case PCI_COMMAND: + { + u32 old = bridge->command; + bridge->command = value & 0xffff; + if ((old ^ bridge->command) & PCI_COMMAND_IO) + mvebu_pcie_handle_iobase_change(port); + if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) + mvebu_pcie_handle_membase_change(port); break; + } case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;