From patchwork Tue Nov 26 21:10:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 3241341 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 75EC6C045B for ; Tue, 26 Nov 2013 21:11:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3109620465 for ; Tue, 26 Nov 2013 21:11:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C6C5A2045B for ; Tue, 26 Nov 2013 21:11:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932604Ab3KZVLU (ORCPT ); Tue, 26 Nov 2013 16:11:20 -0500 Received: from mail-out.m-online.net ([212.18.0.10]:38664 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932499Ab3KZVLT (ORCPT ); Tue, 26 Nov 2013 16:11:19 -0500 Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3dTd860DMzz3hkKR; Tue, 26 Nov 2013 22:11:18 +0100 (CET) X-Auth-Info: TXJXV1H/Ucm+3Cb3+EfRxmVTL0q50VcivLBnBj4Ovyg= Received: from chi.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3dTd852D4jzbbjk; Tue, 26 Nov 2013 22:11:17 +0100 (CET) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: linux-pci@vger.kernel.org, Marek Vasut , Bjorn Helgaas , Frank Li , Harro Haan , Jingoo Han , Mohit KUMAR , Pratyush Anand , Richard Zhu , Sascha Hauer , Sean Cross , Shawn Guo , Siva Reddy Kallam , Srikanth T Shivanand , Tim Harvey , Troy Kisky , Yinghai Lu Subject: [PATCH 3/7] PCI: imx6: Fix waiting for link up Date: Tue, 26 Nov 2013 22:10:44 +0100 Message-Id: <1385500248-6551-3-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1385500248-6551-1-git-send-email-marex@denx.de> References: <1385500248-6551-1-git-send-email-marex@denx.de> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP While waiting for the PHY to report the PCIe link is up, we might hit a situation where the link training is still in progress, while the PHY already reports the link is up. Add additional check for this condition. Signed-off-by: Marek Vasut Cc: Bjorn Helgaas Cc: Frank Li Cc: Harro Haan Cc: Jingoo Han Cc: Mohit KUMAR Cc: Pratyush Anand Cc: Richard Zhu Cc: Sascha Hauer Cc: Sean Cross Cc: Shawn Guo Cc: Siva Reddy Kallam Cc: Srikanth T Shivanand Cc: Tim Harvey Cc: Troy Kisky Cc: Yinghai Lu --- drivers/pci/host/pci-imx6.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 52027ad..4d5be4e 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -48,6 +48,8 @@ struct imx6_pcie { #define PL_OFFSET 0x700 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 @@ -338,10 +340,17 @@ static int imx6_pcie_link_up(struct pcie_port *pp) { u32 rc, ltssm, rx_valid, temp; - /* link is debug bit 36, debug register 1 starts at bit 32 */ - rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); - if (rc) - return -EAGAIN; + /* + * Test if the PHY reports that the link is up and also that + * the link training finished. It might happen that the PHY + * reports the link is already up, but the link training bit + * is still set, so make sure to check the training is done + * as well here. + */ + rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); + if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) && + !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) + return 1; /* * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.