From patchwork Fri Dec 6 20:22:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 3299451 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EA10FC0D4A for ; Fri, 6 Dec 2013 20:22:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C094C204AF for ; Fri, 6 Dec 2013 20:22:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C023220454 for ; Fri, 6 Dec 2013 20:22:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755025Ab3LFUW4 (ORCPT ); Fri, 6 Dec 2013 15:22:56 -0500 Received: from aserp1040.oracle.com ([141.146.126.69]:47102 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754156Ab3LFUWz (ORCPT ); Fri, 6 Dec 2013 15:22:55 -0500 Received: from acsinet21.oracle.com (acsinet21.oracle.com [141.146.126.237]) by aserp1040.oracle.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.1) with ESMTP id rB6KMn0A018601 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 6 Dec 2013 20:22:50 GMT Received: from aserz7022.oracle.com (aserz7022.oracle.com [141.146.126.231]) by acsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id rB6KMmWI011946 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Dec 2013 20:22:49 GMT Received: from abhmp0012.oracle.com (abhmp0012.oracle.com [141.146.116.18]) by aserz7022.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id rB6KMmMP008817; Fri, 6 Dec 2013 20:22:48 GMT Received: from linux-siqj.site (/10.132.126.191) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 06 Dec 2013 12:22:48 -0800 From: Yinghai Lu To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, Yinghai Lu , Kenji Kaneshige , Subject: [PATCH] PCI, pciehp: Turn on link a while to workaround presense detection Date: Fri, 6 Dec 2013 12:22:37 -0800 Message-Id: <1386361357-7767-1-git-send-email-yinghai@kernel.org> X-Mailer: git-send-email 1.8.4 X-Source-IP: acsinet21.oracle.com [141.146.126.237] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP During hotplug test on platform, found slot status register does not report present status correctly. That present bit does not get cleared even after that card is removed. That problem is caused by commit: | commit 2debd9289997fc5d1c0043b41201a8b40d5e11d0 | | PCI: pciehp: Disable/enable link during slot power off/on It looks like chipset bug, that PresDet bit is "OR" operation between sideband input from FPGA, and chipset inband detection from pcie link. It does not like if we disable pcie link at first and power off other side device, and it has input from inband detection always 1. Workaround: Try turn on link a while after power off. After this patch, PresDet report correct status when removing or adding card later. Signed-off-by: Yinghai Lu Cc: Kenji Kaneshige Cc: 3.4+ --- drivers/pci/hotplug/pciehp_hpc.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-2.6/drivers/pci/hotplug/pciehp_hpc.c =================================================================== --- linux-2.6.orig/drivers/pci/hotplug/pciehp_hpc.c +++ linux-2.6/drivers/pci/hotplug/pciehp_hpc.c @@ -637,6 +637,15 @@ int pciehp_power_off_slot(struct slot * } ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); + + /* + * Enable link for a while so chipset could settle down + * inband presence detection logic + */ + pciehp_link_enable(ctrl); + msleep(20); + pciehp_link_disable(ctrl); + return 0; }