From patchwork Mon Dec 9 23:57:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nat Gurumoorthy X-Patchwork-Id: 3313711 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B2190C0D4A for ; Mon, 9 Dec 2013 23:58:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8BC5A202E5 for ; Mon, 9 Dec 2013 23:58:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7F7B820274 for ; Mon, 9 Dec 2013 23:58:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751350Ab3LIX6E (ORCPT ); Mon, 9 Dec 2013 18:58:04 -0500 Received: from mail-oa0-f74.google.com ([209.85.219.74]:64677 "EHLO mail-oa0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751061Ab3LIX6C (ORCPT ); Mon, 9 Dec 2013 18:58:02 -0500 Received: by mail-oa0-f74.google.com with SMTP id o6so860029oag.3 for ; Mon, 09 Dec 2013 15:58:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=8rg0oln0IUGg9NGg1Pnh6LpowRVdRut/rxdggbP5HI0=; b=am28XbuUxUiKBxsyG9AN9HlBBaRaWDXWNBWttw4q10ogcjzv6daT2cx7mvznUR+O8f qpl/UH/3maxk+6KkZs3GBD8l/EaZ7RQs07sUtoGtGipGVLVVmq5xxKOGpwT8rpF8SCkv Ea8RJ9L+mX+oWRhHqKfz76ox1CmN1OXLfDuDee/kAM9B5GBK/i2NKNnxftmXLJJoAfbQ hjVCDrXr7vM6VhTteCkKsvXdwNYSCcGxvhx59dwt/y0T6p7vYg6AqtcSfOQOKnWSsm8t dErQN0plpCajG/kt7A7gX5WTC6YXYgn9kFJM0mlNW7N7sf2b69wsQPM7YbBf2lC48ecQ TE0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8rg0oln0IUGg9NGg1Pnh6LpowRVdRut/rxdggbP5HI0=; b=L3uVk3MW4hyytulrxEpvu823pqfz035nm9ZDxU1EEZ5zcuj6mvYJ4x49eCaNXKgi9v PhUNFeS/tlKRcB8ZnBo0AmfFmcTG65Pqxpz7rusG0qRBAJTCLAutRvl+B6tM27ptitO/ 7bcWWf8LOOBCAb7lcnJzPf1ORj3dtcBJ/lxQBBmvL0o9VheetO5nXPJY/DhelfR7xhyG M2bPuCK06ExGqWEH/3/UwsIgUc6oRfm2n6FT3MYZkG3LRK7HngdPDdSFyIHcct7mXSsI nwOseRdA9ajV/sP7Qq2HUKGBtzl4WMDJlCaZJDiEfHzg9Lqiyhh5Yl6TIEAaGAHCHt+7 Ke6g== X-Gm-Message-State: ALoCoQn2ZARV58r1ki+crn89i5usxmPlxPaFtbEiVFElsD2CFEFZL019SwaZ5BlQAPqHxtA3INEWOTEhahEQZ0RQYvWR/5SOtt69E8t6flGZvlZk+68cJlDlxTsyj5jPmmaLkaicr8D+YAsE4gsEWgkIo9aXMtHcF3Bky2I56fTdQxMk0hLXXu8frSsSNSpAgaQSka0QDCH8znQN/5q/LM3AyRcXMlC4CA== X-Received: by 10.182.126.137 with SMTP id my9mr7783019obb.13.1386633481478; Mon, 09 Dec 2013 15:58:01 -0800 (PST) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id h47si16424230yhn.0.2013.12.09.15.58.01 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Dec 2013 15:58:01 -0800 (PST) Received: from natg-linux.mtv.corp.google.com (natg-linux.mtv.corp.google.com [172.18.64.23]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 3581831C1B6; Mon, 9 Dec 2013 15:58:01 -0800 (PST) Received: by natg-linux.mtv.corp.google.com (Postfix, from userid 128070) id BB18020176; Mon, 9 Dec 2013 15:58:00 -0800 (PST) From: Nat Gurumoorthy To: nsujir@broadcom.com, mchan@broadcom.com, bhelgaas@google.com Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Nat Gurumoorthy Subject: [PATCH] PCI: Add quirk to initialize REG_BASE_ADDR to 0 for Broadcom TIGON3 chips. Date: Mon, 9 Dec 2013 15:57:22 -0800 Message-Id: <1386633442-12509-1-git-send-email-natg@google.com> X-Mailer: git-send-email 1.8.5.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The new tg3 driver leaves REG_BASE_ADDR (PCI config offset 120) uninitialized. From power on reset this register may have garbage in it. The Register Base Address register defines the device local address of a register. The data pointed to by this location is read or written using the Register Data register (PCI config offset 128). When REG_BASE_ADDR has garbage any read or write of Register Data Register (PCI 128) will cause the PCI bus to lock up. The TCO watchdog will fire and bring down the system. Signed-off-by: --- drivers/pci/quirks.c | 138 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 3a02717..b9a289b 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3461,3 +3461,141 @@ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) return -ENOTTY; } + +/* + * This is a quirk is to initialize REG_BASE_ADDR at PCI config offset 120 + * to 0 for all Broadcom devices controlled by the TIGON3 driver. + */ +static void tg3_init_reg_base_addr(struct pci_dev *dev) +{ + pci_write_config_dword(dev, 120, 0); +} + + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SYSKONNECT, + PCI_DEVICE_ID_SYSKONNECT_9DXX, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SYSKONNECT, + PCI_DEVICE_ID_SYSKONNECT_9MXX, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3, + tg3_init_reg_base_addr); +DECLARE_PCI_FIXUP_EARLY(0x10cf, 0x11a2, tg3_init_reg_base_addr);