From patchwork Wed Feb 19 20:22:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 3682921 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7EC049F2EC for ; Wed, 19 Feb 2014 20:22:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8DBDE201CD for ; Wed, 19 Feb 2014 20:22:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9E85B201FE for ; Wed, 19 Feb 2014 20:22:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755050AbaBSUWX (ORCPT ); Wed, 19 Feb 2014 15:22:23 -0500 Received: from mail-pb0-f41.google.com ([209.85.160.41]:60303 "EHLO mail-pb0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754569AbaBSUWV (ORCPT ); Wed, 19 Feb 2014 15:22:21 -0500 Received: by mail-pb0-f41.google.com with SMTP id up15so879813pbc.28 for ; Wed, 19 Feb 2014 12:22:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=crv/fYegYSmz5PSyazMg0+B0YqrfWaqJLpxtz1kwCCA=; b=aKLcGXkiv03cHB3BFB+NdXsSb/TMvkvWLqezStyDDvUSt6zl/VAvrn4aWn81Dtai7a e+DDg6Mh9hNbkwcTq/2o1+W5DBkhMg7Vt61x7LnMXhaAGOBNEDBh/JUnGM/5mDXLByG1 8jrgsTbOyXVrVgBxITttXP5aJVNN5s9H6rUmVeQ2+z8K16B2ZoxGqUlQr72tu8LiMGeR UT8LBv2f/XBZpgqksZe8ghz2HhSWkcvQ1Jv1UHc+K2Gv6Nbo2CPqLvgAU05oYK0ALCDf FlijMie1hmJW0XlVq5FrX1tQ4L4CsmajO2Y5R+N9PPs51iswxLjgyZp4fgDd/sDgcHyU o+6A== X-Gm-Message-State: ALoCoQmiQFf/NH2oQ8m/BRhpOUO9r/Bqo1U7hfP9UToSxNmoauZ13l6HWor/SQpmOQcvSGxAWsfC X-Received: by 10.66.142.107 with SMTP id rv11mr42237972pab.17.1392841340613; Wed, 19 Feb 2014 12:22:20 -0800 (PST) Received: from officeserver-2 ([63.226.49.26]) by mx.google.com with ESMTPSA id ix2sm363780pbc.45.2014.02.19.12.22.18 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 19 Feb 2014 12:22:19 -0800 (PST) Received: from tkisky by officeserver-2 with local (Exim 4.80) (envelope-from ) id 1WGDez-0003Wm-9L; Wed, 19 Feb 2014 13:22:25 -0700 From: Troy Kisky To: bhelgaas@google.com, s.hauer@pengutronix.de, marex@denx.de Cc: linux-pci@vger.kernel.org, kernel@pengutronix.de, r65037@freescale.com, shawn.guo@linaro.org, linux-arm-kernel@lists.infradead.org, Troy Kisky Subject: [PATCH 1/1] pci-imx6.c: wait for retraining Date: Wed, 19 Feb 2014 13:22:18 -0700 Message-Id: <1392841338-13527-1-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.8.1.2 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marek Vasut This patch handles the case where the PCIe link is up and running, yet drops into the LTSSM training mode. The link spends short time in the LTSSM training mode, but the current code can misinterpret it as the link being stalled. Waiting for the LTSSM training to complete fixes the issue. Quoting Sascha, "This is broken since commit e6daf4a5e1b813bc7f85507ec83b8c2452c121e6 PCI: imx6: Report "link up" only after link training completes The designware driver changes the PORT_LOGIC_SPEED_CHANGE bit in dw_pcie_host_init() which causes the link to be retrained. During the next call to dw_pcie_rd_conf() the link is then reported being down and the function returns PCIBIOS_DEVICE_NOT_FOUND resulting in nonfunctioning PCIe." Signed-off-by: Marek Vasut Tested-by: Troy Kisky Tested-by: Sascha Hauer Acked-by: Shawn Guo Signed-off-by: Troy Kisky --- drivers/pci/host/pci-imx6.c | 47 ++++++++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index e8663a8..ee08250 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -424,20 +424,40 @@ static void imx6_pcie_reset_phy(struct pcie_port *pp) static int imx6_pcie_link_up(struct pcie_port *pp) { - u32 rc, ltssm, rx_valid; + u32 rc, debug_r0, rx_valid; + int count = 5; /* - * Test if the PHY reports that the link is up and also that - * the link training finished. It might happen that the PHY - * reports the link is already up, but the link training bit - * is still set, so make sure to check the training is done - * as well here. + * Test if the PHY reports that the link is up and also that the LTSSM + * training finished. There are three possible states of the link when + * this code is called: + * 1) The link is DOWN (unlikely) + * The link didn't come up yet for some reason. This usually means + * we have a real problem somewhere. Reset the PHY and exit. This + * state calls for inspection of the DEBUG registers. + * 2) The link is UP, but still in LTSSM training + * Wait for the training to finish, which should take a very short + * time. If the training does not finish, we have a problem and we + * need to inspect the DEBUG registers. If the training does finish, + * the link is up and operating correctly. + * 3) The link is UP and no longer in LTSSM training + * The link is up and operating correctly. */ - rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); - if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) && - !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) - return 1; - + while (1) { + rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); + if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP)) + break; + if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) + return 1; + if (!count--) + break; + dev_dbg(pp->dev, "Link is up, but still in training\n"); + /* + * Wait a little bit, then re-check if the link finished + * the training. + */ + usleep_range(1000, 2000); + } /* * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). @@ -446,15 +466,16 @@ static int imx6_pcie_link_up(struct pcie_port *pp) * to gen2 is stuck */ pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); - ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F; + debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0); if (rx_valid & 0x01) return 0; - if (ltssm != 0x0d) + if ((debug_r0 & 0x3f) != 0x0d) return 0; dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); + dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc); imx6_pcie_reset_phy(pp);