From patchwork Thu Jul 3 20:46:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 4476891 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E741CBEEAA for ; Thu, 3 Jul 2014 20:46:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 296032026F for ; Thu, 3 Jul 2014 20:46:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 569D320253 for ; Thu, 3 Jul 2014 20:46:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753674AbaGCUqv (ORCPT ); Thu, 3 Jul 2014 16:46:51 -0400 Received: from aserp1040.oracle.com ([141.146.126.69]:32376 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751844AbaGCUqv (ORCPT ); Thu, 3 Jul 2014 16:46:51 -0400 Received: from acsinet21.oracle.com (acsinet21.oracle.com [141.146.126.237]) by aserp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id s63KkkJK011059 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 3 Jul 2014 20:46:46 GMT Received: from userz7021.oracle.com (userz7021.oracle.com [156.151.31.85]) by acsinet21.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id s63KkjF8021667 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL); Thu, 3 Jul 2014 20:46:46 GMT Received: from abhmp0020.oracle.com (abhmp0020.oracle.com [141.146.116.26]) by userz7021.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id s63KkiPv019805; Thu, 3 Jul 2014 20:46:45 GMT Received: from linux-siqj.site (/10.132.126.31) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 03 Jul 2014 13:46:44 -0700 From: Yinghai Lu To: Bjorn Helgaas , Guo Chao Cc: linux-pci@vger.kernel.org, Yinghai Lu Subject: [PATCH v4 2/3] PCI: Fix bus align checking with 32bit bridge pref Date: Thu, 3 Jul 2014 13:46:18 -0700 Message-Id: <1404420379-20983-2-git-send-email-yinghai@kernel.org> X-Mailer: git-send-email 1.8.4.5 In-Reply-To: <1404420379-20983-1-git-send-email-yinghai@kernel.org> References: <1404420379-20983-1-git-send-email-yinghai@kernel.org> X-Source-IP: acsinet21.oracle.com [141.146.126.237] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the bridge does not support 64bit pref mmio, we should still keep align to be 2G as old time. So add mmio64 mask checking, keep that 2G checking in the loop. Signed-off-by: Yinghai Lu --- drivers/pci/setup-bus.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-2.6/drivers/pci/setup-bus.c =================================================================== --- linux-2.6.orig/drivers/pci/setup-bus.c +++ linux-2.6/drivers/pci/setup-bus.c @@ -930,10 +930,17 @@ static int pbus_size_mem(struct pci_bus struct resource *b_res = find_free_bus_resource(bus, mask | IORESOURCE_PREFETCH, type); resource_size_t children_add_size = 0; + unsigned int mem64_mask; if (!b_res) return -ENOSPC; + mem64_mask = b_res->flags & IORESOURCE_MEM_64; + + /* kernel does not support 64bit res */ + if (sizeof(resource_size_t) == 4) + mem64_mask &= ~IORESOURCE_MEM_64; + memset(aligns, 0, sizeof(aligns)); max_order = 0; size = 0; @@ -970,12 +977,14 @@ static int pbus_size_mem(struct pci_bus order = __ffs(align) - 20; if (order < 0) order = 0; - if (order >= ARRAY_SIZE(aligns)) { + if (order >= ARRAY_SIZE(aligns) || + (!mem64_mask && order > 11 /* 2Gb */)) { dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", i, r, (unsigned long long) align); r->flags = 0; continue; } + size += r_size; /* Exclude ranges with size > align from calculation of the alignment. */