From patchwork Wed Jul 23 17:52:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 4612371 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9E946C0514 for ; Wed, 23 Jul 2014 17:53:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DA462201BF for ; Wed, 23 Jul 2014 17:53:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0639F20154 for ; Wed, 23 Jul 2014 17:53:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932600AbaGWRxO (ORCPT ); Wed, 23 Jul 2014 13:53:14 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:42412 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932289AbaGWRxN (ORCPT ); Wed, 23 Jul 2014 13:53:13 -0400 Received: from dude.hi.pengutronix.de ([10.1.0.7] helo=dude.pengutronix.de) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1XA0ic-0000bv-Az; Wed, 23 Jul 2014 19:52:46 +0200 From: Lucas Stach To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, Richard Zhu , Mohit Kumar , Jingoo Han , Marek Vasut , Kishon Vijay Abraham I , kernel@pengutronix.de Subject: [PATCH 1/4] PCI: designware: start parsing bus-range Date: Wed, 23 Jul 2014 19:52:38 +0200 Message-Id: <1406137961-14684-2-git-send-email-l.stach@pengutronix.de> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1406137961-14684-1-git-send-email-l.stach@pengutronix.de> References: <1406137961-14684-1-git-send-email-l.stach@pengutronix.de> X-SA-Exim-Connect-IP: 10.1.0.7 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-pci@vger.kernel.org Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows to explicitly specify the covered bus numbers in the devicetree, which will come in handy once we see a SoC with more than one PCIe host controller instance. Previously the driver relied on the behavior of pci_scan_root_bus() to fill in a range of 0x00-0xff if no valid range was found. We fall back to the same range if no valid DT entry was found to keep backwards compatibility, but now do it explicitly. Signed-off-by: Lucas Stach Reviewed-by: Pratyush Anand --- Documentation/devicetree/bindings/pci/designware-pcie.txt | 3 +++ drivers/pci/host/pcie-designware.c | 13 ++++++++++++- drivers/pci/host/pcie-designware.h | 1 + 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index ed0d9b9fff2b..9f4faa8e8d00 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -23,3 +23,6 @@ Required properties: Optional properties: - reset-gpio: gpio pin number of power good signal +- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to + specify this property, to keep backwards compatibility a range of 0x00-0xff + is assumed if not present) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 52bd3a143563..b13a830c8b0f 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -425,7 +425,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) struct resource *cfg_res; u32 val, na, ns; const __be32 *addrp; - int i, index; + int i, index, ret; /* Find the address cell size and the number of cells in order to get * the untranslated address. @@ -500,6 +500,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } } + ret = of_pci_parse_bus_range(np, &pp->busn); + if (ret < 0) { + dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default [0x00-0xff]\n", + ret); + pp->busn.name = np->name; + pp->busn.start = 0; + pp->busn.end = 0xff; + pp->busn.flags = IORESOURCE_BUS; + } + if (!pp->dbi_base) { pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, resource_size(&pp->cfg)); @@ -781,6 +791,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr; pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); + pci_add_resource(&sys->resources, &pp->busn); return 1; } diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index daf81f922cda..9a09633ecdf8 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -48,6 +48,7 @@ struct pcie_port { struct resource cfg; struct resource io; struct resource mem; + struct resource busn; struct pcie_port_info config; int irq; u32 lanes;