From patchwork Sat Jul 26 03:08:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 4626501 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DDF89C0338 for ; Sat, 26 Jul 2014 02:47:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E5CB2020F for ; Sat, 26 Jul 2014 02:47:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DB90120219 for ; Sat, 26 Jul 2014 02:47:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760427AbaGZCoB (ORCPT ); Fri, 25 Jul 2014 22:44:01 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:6656 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752850AbaGZCnt (ORCPT ); Fri, 25 Jul 2014 22:43:49 -0400 Received: from 172.24.2.119 (EHLO szxeml419-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BXE25887; Sat, 26 Jul 2014 10:43:42 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml419-hub.china.huawei.com (10.82.67.158) with Microsoft SMTP Server id 14.3.158.1; Sat, 26 Jul 2014 10:43:31 +0800 From: Yijing Wang To: CC: Xinwei Hu , Wuyun , "Bjorn Helgaas" , , , "James E.J. Bottomley" , "Marc Zyngier" , , Russell King , , , , Hanjun Guo , Yijing Wang Subject: [RFC PATCH 04/11] PCI/MSI: Move MSIX table address mapping out of msix_capability_init Date: Sat, 26 Jul 2014 11:08:41 +0800 Message-ID: <1406344128-27055-5-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1406344128-27055-1-git-send-email-wangyijing@huawei.com> References: <1406344128-27055-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move MSIX table address mapping work to PCI MSIX layer. Some Non-PCI MSI device will do their address mapping work before enable MSIX capability or their MSIX table address is within device address block. So Move address mapping stuff out of the generic MSIX core. This is prepartion for generic MSI drvier. Suggested-by: Yun Wu Signed-off-by: Yijing Wang --- drivers/pci/msi.c | 25 +++++++++++++------------ 1 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index d5c8e56..116383c 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -668,8 +668,8 @@ static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) u32 table_offset; u8 bir; - pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, - &table_offset); + pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, + &table_offset); bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); table_offset &= PCI_MSIX_TABLE_OFFSET; phys_addr = pci_resource_start(dev, bir) + table_offset; @@ -734,22 +734,14 @@ static void msix_program_entries(struct pci_dev *dev, * single MSI-X irq. A return of zero indicates the successful setup of * requested MSI-X entries with allocated irqs or non-zero for otherwise. **/ -static int msix_capability_init(struct pci_dev *dev, +static int msix_capability_init(struct pci_dev *dev, void __iomem *base, struct msix_entry *entries, int nvec) { int ret; - u16 control; - void __iomem *base; /* Ensure MSI-X is disabled while it is set up */ msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); - pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); - /* Request & Map MSI-X table region */ - base = msix_map_region(dev, msix_table_size(control)); - if (!base) - return -ENOMEM; - ret = msix_setup_entries(dev, base, entries, nvec); if (ret) return ret; @@ -948,6 +940,8 @@ int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) { int status, nr_entries; int i, j; + void __iomem *base; + u16 control; if (!entries || !dev->msix_cap || dev->current_state != PCI_D0) return -EINVAL; @@ -978,7 +972,14 @@ int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); return -EINVAL; } - status = msix_capability_init(dev, entries, nvec); + + /* Request & Map MSI-X table region */ + pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); + base = msix_map_region(dev, msix_table_size(control)); + if (!base) + return -ENOMEM; + + status = msix_capability_init(dev, base, entries, nvec); return status; } EXPORT_SYMBOL(pci_enable_msix);