From patchwork Fri Aug 8 06:36:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 4694081 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 659AF9F375 for ; Fri, 8 Aug 2014 06:36:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8D0B82017D for ; Fri, 8 Aug 2014 06:36:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1E0F20158 for ; Fri, 8 Aug 2014 06:36:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755914AbaHHGgu (ORCPT ); Fri, 8 Aug 2014 02:36:50 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:38043 "EHLO mail-pd0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755870AbaHHGgt (ORCPT ); Fri, 8 Aug 2014 02:36:49 -0400 Received: by mail-pd0-f176.google.com with SMTP id y10so6477800pdj.7 for ; Thu, 07 Aug 2014 23:36:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=VIlZ6FHoynkF7mUfdWc7oCm6TsUFjEv+j8VNRm5yRlE=; b=L6763Uj6kQClLx6fIqkw8gT3amu7TGlCfRp/TaZUu63gcSrwNoo5P0Arp7KvPJ1GKN BiQdG92ZJbczJyqQpgQM8kZzcWDu/LrVqIGuIqr6gM451e2v0ejkEtO5ZjkSCgPaE9BP VbLDVmvG8GzWbKfCaCh2vgggYZz9vm0+hYbg7m5j5NuP0FTi9Eu8AOVmLdPsDob54l+y CdK/5BGt9APTv+x5mnm51oLvsTpvgWKdW7may8Roy6+qtZYx0Yl7VJ6yN7EXVbW/0Dak A0me5t2h1t3QYPvuqTazPPRGiwKI21HyiB6EkrjsRGxdf+8j5NOWVX8mG6AL8YME3QnG tazQ== X-Gm-Message-State: ALoCoQmBdfWIqd54QpweRhLwB34GNHCNDTh5X1cOlpW2thgSqcFPoole8I1JenFg3zNlCaXGEeC9 X-Received: by 10.68.232.163 with SMTP id tp3mr22216237pbc.97.1407479809320; Thu, 07 Aug 2014 23:36:49 -0700 (PDT) Received: from tharvey-gw.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id fx13sm2717467pdb.64.2014.08.07.23.36.48 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 07 Aug 2014 23:36:48 -0700 (PDT) From: Tim Harvey To: l.stach@pengutronix.de Cc: Fabio Estevam , shawn.guo@freescale.com, stable@vger.kernel.org, marex@denx.de, bhelgaas@google.com, linux-pci@vger.kernel.org Subject: [PATCH] PCI: imx6: fix occasional link failure Date: Thu, 7 Aug 2014 23:36:40 -0700 Message-Id: <1407479800-6730-1-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.8.3.2 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey Tested-by: Fabio Estevam Acked-by: Marek Vasut --- drivers/pci/host/pci-imx6.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 1be6073..9b6bab9 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -256,11 +256,6 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); int ret; - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - ret = clk_prepare_enable(imx6_pcie->pcie_phy); if (ret) { dev_err(pp->dev, "unable to enable pcie_phy clock\n"); @@ -282,6 +277,12 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) /* allow the clocks to stabilize */ usleep_range(200, 500); + /* power up core phy and enable ref clock */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);