From patchwork Wed Aug 13 06:22:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gong X-Patchwork-Id: 4716521 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8996E9F319 for ; Wed, 13 Aug 2014 06:56:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC5DF201C0 for ; Wed, 13 Aug 2014 06:56:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5B82B201B9 for ; Wed, 13 Aug 2014 06:56:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751269AbaHMGzN (ORCPT ); Wed, 13 Aug 2014 02:55:13 -0400 Received: from mga11.intel.com ([192.55.52.93]:4194 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751227AbaHMGzM (ORCPT ); Wed, 13 Aug 2014 02:55:12 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 12 Aug 2014 23:55:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,855,1400050800"; d="scan'208";a="575970032" Received: from gchen-sby.bj.intel.com (HELO localhost) ([10.238.158.82]) by fmsmga001.fm.intel.com with ESMTP; 12 Aug 2014 23:55:04 -0700 From: "Chen, Gong" To: bhelgaas@google.com, rdunlap@infradead.org Cc: bp@alien8.de, tony.luck@intel.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, "Chen, Gong" Subject: [RESEND RFC 5/5] PCIe, AER: Update initial value of UC error mask Date: Wed, 13 Aug 2014 02:22:41 -0400 Message-Id: <1407910961-7798-6-git-send-email-gong.chen@linux.intel.com> X-Mailer: git-send-email 2.0.0.rc2 In-Reply-To: <1407910961-7798-1-git-send-email-gong.chen@linux.intel.com> References: <1407910961-7798-1-git-send-email-gong.chen@linux.intel.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In PCI-e SPEC r3.0, BIT 0 of Uncorrectable Error Status Register is redefined and it has an explicit requirement that when writing this field, a value of 1b is the only choice. So change previous initial maks from 0 to 1. Signed-off-by: Chen, Gong --- NOTE: After scratching all use cases, this is the most obvious use case to violate the SPEC. Most of use cases just read first and then overwrite for clear purpose. Even so, such fix is obvious to not compatiable with previous SPEC definition. Do we need a dirty hack? arch/mips/pci/pci-octeon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 59cccd95688b..f1bfdc201297 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -134,7 +134,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) dconfig); /* Enable reporting of all uncorrectable errors */ /* Uncorrectable Error Mask - turned on bits disable errors */ - pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 1); /* * Leave severity at HW default. This only controls if * errors are reported as uncorrectable or