From patchwork Sat Sep 6 00:25:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Inamdar X-Patchwork-Id: 4856771 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 61EA09F32F for ; Sat, 6 Sep 2014 00:33:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 972D220211 for ; Sat, 6 Sep 2014 00:33:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 968BD201BF for ; Sat, 6 Sep 2014 00:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751647AbaIFAdh (ORCPT ); Fri, 5 Sep 2014 20:33:37 -0400 Received: from exprod5og106.obsmtp.com ([64.18.0.182]:37967 "HELO exprod5og106.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1751321AbaIFAdh (ORCPT ); Fri, 5 Sep 2014 20:33:37 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]) (using TLSv1) by exprod5ob106.postini.com ([64.18.4.12]) with SMTP ID DSNKVApWYe2dH/KmDDBFqoeneervkubLm5Mh@postini.com; Fri, 05 Sep 2014 17:33:37 PDT Received: by mail-pd0-f182.google.com with SMTP id fp1so16690642pdb.41 for ; Fri, 05 Sep 2014 17:33:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZddbfuopI4vfjPk24+dBATF2xwq5Hu2Ub/8xbbn7xnM=; b=LwVPwC8PmfaVucsSYzmpXQ2jjVvUSRQ4W/unn/uRTmPi94eCMnwCNT3DJP20lfsmgy Uogu3DveIIV7Y/cWzpv2QDPYBxsE4uWq4LvcvoeiMFrCVpzCP/EX4PwQYu39MEYjcc6+ dkk7ujAPoTg9l2Uxc4rZqhBt0ieWPXsqeek7AQn00FBQQgd1/Uo8wu/vcB+SXx3Mj7eV Ed7elJjURrJ3STaee+o2SR1wLJ3d3uP2kM0V+hT1qNLCoOWfZSpUXuoSqiaRnc5z8bE2 SOCG3VmG0GguR+A7MbFK/p1bxu1hYGMEliCPQ2aPjAuBFNsvDStAd2zNF/I3x8YDHhDE CidQ== X-Received: by 10.66.145.167 with SMTP id sv7mr26235723pab.5.1409963138998; Fri, 05 Sep 2014 17:25:38 -0700 (PDT) X-Gm-Message-State: ALoCoQl98G0Rera9R3++QS8eEEcJBEX0REHK1LLy1NcGdeROW/RgRS7BkKC4TzEuGwIKIVc2mKFfRdzg1Ryxv1X5PM/HORNlhZ/CtHhNTqtA7+MESG7Jfr1JLKbZc6wSkvGArQz2FHt9pOuCC1rKR1+xnLXXGTcGTA== X-Received: by 10.66.145.167 with SMTP id sv7mr26235715pab.5.1409963138910; Fri, 05 Sep 2014 17:25:38 -0700 (PDT) Received: from svdclab-13-11.amcc.com (67-207-112-226.static.wiline.com. [67.207.112.226]) by mx.google.com with ESMTPSA id t4sm2752101pdm.3.2014.09.05.17.25.37 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Sep 2014 17:25:38 -0700 (PDT) From: Tanmay Inamdar To: Bjorn Helgaas , Arnd Bergmann , Jason Gunthorpe , Grant Likely , Rob Herring , Catalin Marinas , Rob Landley , Liviu Dudau Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, patches@apm.com, jcm@redhat.com, Tanmay Inamdar Subject: [PATCH v6 3/4] dt-bindings: pci: xgene pcie device tree bindings Date: Fri, 5 Sep 2014 17:25:42 -0700 Message-Id: <1409963143-11951-4-git-send-email-tinamdar@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1409963143-11951-1-git-send-email-tinamdar@apm.com> References: <1409963143-11951-1-git-send-email-tinamdar@apm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bindings for X-Gene PCIe driver. The driver resides under 'drivers/pci/host/pci-xgene.c' file. Signed-off-by: Tanmay Inamdar --- .../devicetree/bindings/pci/xgene-pci.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xgene-pci.txt diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt new file mode 100644 index 0000000..683a253 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt @@ -0,0 +1,55 @@ +* AppliedMicro X-Gene PCIe interface + +Required properties: +- device_type: set to "pci" +- compatible: should contain "apm,xgene-pcie" to identify the core. +- reg: A list of physical base address and length for each set of controller + registers. Must contain an entry for each entry in the reg-names + property. +- reg-names: Must include the following entries: + "csr": controller configuration registers. + "cfg": pcie configuration space registers. +- #address-cells: set to <3> +- #size-cells: set to <2> +- ranges: ranges for the outbound memory, I/O regions. +- dma-ranges: ranges for the inbound memory regions. +- #interrupt-cells: set to <1> +- interrupt-map-mask and interrupt-map: standard PCI properties + to define the mapping of the PCIe interface to interrupt + numbers. +- clocks: from common clock binding: handle to pci clock. + +Optional properties: +- status: Either "ok" or "disabled". + +Example: + +SoC specific DT Entry: + + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + clocks = <&pcie0clk 0>; + }; + + +Board specific DT Entry: + &pcie0 { + status = "ok"; + };