From patchwork Thu Sep 18 02:08:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suravee Suthikulpanit X-Patchwork-Id: 4928481 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3EB5FBEEA6 for ; Thu, 18 Sep 2014 02:09:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 67D652015D for ; Thu, 18 Sep 2014 02:09:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5294201B9 for ; Thu, 18 Sep 2014 02:09:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757368AbaIRCJB (ORCPT ); Wed, 17 Sep 2014 22:09:01 -0400 Received: from mail-bn1on0146.outbound.protection.outlook.com ([157.56.110.146]:46912 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755836AbaIRCI7 (ORCPT ); Wed, 17 Sep 2014 22:08:59 -0400 Received: from BLUPR02CA031.namprd02.prod.outlook.com (25.160.23.149) by BN1PR02MB197.namprd02.prod.outlook.com (10.242.214.146) with Microsoft SMTP Server (TLS) id 15.0.1029.13; Thu, 18 Sep 2014 02:08:56 +0000 Received: from BN1AFFO11FD022.protection.gbl (2a01:111:f400:7c10::176) by BLUPR02CA031.outlook.office365.com (2a01:111:e400:8ad::21) with Microsoft SMTP Server (TLS) id 15.0.1034.13 via Frontend Transport; Thu, 18 Sep 2014 02:08:56 +0000 Received: from atltwp01.amd.com (165.204.84.221) by BN1AFFO11FD022.mail.protection.outlook.com (10.58.52.82) with Microsoft SMTP Server id 15.0.1029.15 via Frontend Transport; Thu, 18 Sep 2014 02:08:55 +0000 X-WSS-ID: 0NC2RAT-07-FQ4-02 X-M-MSG: Received: from satlvexedge02.amd.com (satlvexedge02.amd.com [10.177.96.29]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.3.1) with ESMTPS id 2BAF7CAE65D; Wed, 17 Sep 2014 21:08:53 -0500 (CDT) Received: from SATLEXDAG02.amd.com (10.181.40.5) by SATLVEXEDGE02.amd.com (10.177.96.29) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 17 Sep 2014 21:09:05 -0500 Received: from ssuthiku-fedora-lt.amd.com (10.180.168.240) by SATLEXDAG02.amd.com (10.181.40.5) with Microsoft SMTP Server id 14.3.195.1; Wed, 17 Sep 2014 22:08:53 -0400 From: To: , , CC: , , , , , , , , , , , "Suravee Suthikulpanit" , Mark Rutland , Marc Zyngier Subject: [PATCH 1/2 V7] irqchip: gic: Add support for multiple MSI for ARM64 Date: Wed, 17 Sep 2014 19:08:25 -0700 Message-ID: <1411006106-17339-2-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1411006106-17339-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1411006106-17339-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(88136002)(50226001)(104166001)(48376002)(50466002)(19580395003)(77096002)(90102001)(62966002)(20776003)(229853001)(83072002)(89996001)(101416001)(92726001)(2201001)(33646002)(4396001)(95666004)(77156001)(87936001)(84676001)(76176999)(64706001)(106466001)(47776003)(74662003)(81342003)(85306004)(19580405001)(31966008)(87286001)(107046002)(21056001)(50986999)(36756003)(79102003)(83322001)(85852003)(92566001)(74502003)(105586002)(97736003)(44976005)(81542003)(77982003)(86152002)(93916002)(46102003)(53416004)(86362001)(80022003)(68736004)(99396002)(2004002); DIR:OUT; SFP:1102; SCL:1; SRVR:BN1PR02MB197; H:atltwp01.amd.com; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 033857D0BD Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; X-OriginatorOrg: amd4.onmicrosoft.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Suravee Suthikulpanit This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Suravee Suthikulpanit --- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/msi.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 arch/arm64/kernel/msi.c diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index df7ef87..a921c42 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -29,6 +29,7 @@ arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o +arm64-obj-$(CONFIG_PCI_MSI) += msi.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/msi.c b/arch/arm64/kernel/msi.c new file mode 100644 index 0000000..a295862 --- /dev/null +++ b/arch/arm64/kernel/msi.c @@ -0,0 +1,41 @@ +/* + * ARM64 architectural MSI implemention + * + * Support for Message Signalelled Interrupts for systems that + * implement ARM Generic Interrupt Controller: GICv2m. + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * Authors: Suravee Suthikulpanit + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +/* + * ARM64 function for seting up MSI irqs. + * Based on driver/pci/msi.c: arch_setup_msi_irqs(). + * + * Note: + * Current implementation assumes that all interrupt controller used in + * ARM64 architecture _MUST_ supports multi-MSI. + */ +int arm64_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +{ + struct msi_desc *entry; + int ret; + + list_for_each_entry(entry, &dev->msi_list, list) { + ret = arch_setup_msi_irq(dev, entry); + if (ret < 0) + return ret; + if (ret > 0) + return -ENOSPC; + } + + return 0; +}