From patchwork Tue Sep 23 04:11:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 4952871 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BEC29BEEA6 for ; Tue, 23 Sep 2014 04:39:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 69E9720221 for ; Tue, 23 Sep 2014 04:39:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F40E62020F for ; Tue, 23 Sep 2014 04:39:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751464AbaIWEjk (ORCPT ); Tue, 23 Sep 2014 00:39:40 -0400 Received: from mail-by2on0144.outbound.protection.outlook.com ([207.46.100.144]:19381 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751012AbaIWEjj (ORCPT ); Tue, 23 Sep 2014 00:39:39 -0400 Received: from DM2PR0301MB0861.namprd03.prod.outlook.com (25.160.215.147) by DM2PR0301MB0637.namprd03.prod.outlook.com (25.160.96.11) with Microsoft SMTP Server (TLS) id 15.0.1034.13; Tue, 23 Sep 2014 04:39:36 +0000 Received: from CO2PR03CA0028.namprd03.prod.outlook.com (10.141.194.155) by DM2PR0301MB0861.namprd03.prod.outlook.com (25.160.215.147) with Microsoft SMTP Server (TLS) id 15.0.1039.15; Tue, 23 Sep 2014 04:39:35 +0000 Received: from BL2FFO11FD046.protection.gbl (2a01:111:f400:7c09::103) by CO2PR03CA0028.outlook.office365.com (2a01:111:e400:1414::27) with Microsoft SMTP Server (TLS) id 15.0.1034.13 via Frontend Transport; Tue, 23 Sep 2014 04:39:35 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD046.mail.protection.outlook.com (10.173.161.208) with Microsoft SMTP Server (TLS) id 15.0.1029.15 via Frontend Transport; Tue, 23 Sep 2014 04:39:34 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s8N4dWHh020480; Mon, 22 Sep 2014 21:39:33 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id BFE5F1AE200; Tue, 23 Sep 2014 12:11:39 +0800 (CST) From: Richard Zhu To: CC: , , , , , Richard Zhu Subject: [PATCH v2 3/5] PCI: imx6: update dts and binding for imx6sx pcie Date: Tue, 23 Sep 2014 12:11:36 +0800 Message-ID: <1411445498-20250-4-git-send-email-r65037@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1411445498-20250-1-git-send-email-r65037@freescale.com> References: <1411445498-20250-1-git-send-email-r65037@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(42186005)(48376002)(89996001)(52956003)(50466002)(83072002)(85852003)(104166001)(87286001)(88136002)(87936001)(46386002)(85306004)(45336002)(120916001)(21056001)(92726001)(93916002)(10300001)(84676001)(92566001)(76176999)(76482002)(69596002)(50986999)(68736004)(83322001)(31966008)(44976005)(19580405001)(19580395003)(16796002)(6806004)(101416001)(4396001)(102836001)(50226001)(99396002)(64706001)(47776003)(20776003)(79102003)(80022003)(46102003)(77982003)(74662003)(74502003)(81542003)(81342003)(97736003)(90102001)(107046002)(2351001)(229853001)(36756003)(77156001)(110136001)(33646002)(103686003)(105586002)(95666004)(62966002)(81156004)(106466001)(77096002)(32563001)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0861; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0861; X-Forefront-PRVS: 0343AC1D30 Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0637; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - imx6sx pcie has its own power regulator. add the pcie power suppy into dts and binding. - enable pcie on imx6sx soc. Signed-off-by: Richard Zhu --- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++- arch/arm/boot/dts/imx6sx-sdb.dts | 13 +++++++++ arch/arm/boot/dts/imx6sx.dtsi | 33 +++++++++++++--------- arch/arm/mach-imx/Kconfig | 1 + 4 files changed, 36 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 9455fd0..d3b5704 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "fsl,imx6q-pcie" +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie" - reg: base addresse and length of the pcie controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -12,6 +12,7 @@ Required properties: - "msi": The interrupt that is asserted when an MSI is received - clock-names: Must include the following additional entries: - "pcie_phy" +- regulator: regulator used by imx6sx pcie module. Example: @@ -35,4 +36,5 @@ Example: <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 144>, <&clks 206>, <&clks 189>; clock-names = "pcie", "pcie_bus", "pcie_phy"; + pcie-supply = <®_pcie>; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index a3980d9..2976913 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -251,6 +251,13 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 0 0>; + status = "okay"; +}; + &ssi2 { status = "okay"; }; @@ -365,6 +372,12 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index f4b9da6..4911160 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -689,9 +689,11 @@ }; gpc: gpc@020dc000 { - compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; + compatible = "fsl,imx6sx-gpc", + "fsl,imx6q-gpc", "syscon"; reg = <0x020dc000 0x4000>; interrupts = ; + pcie-supply = <®_pcie>; }; iomuxc: iomuxc@020e0000 { @@ -1188,20 +1190,23 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 - /* downstream I/O */ - 0x81000000 0 0 0x08f80000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + ranges = <0x00000800 0 0x01f00000 0x08f00000 0 0x00080000 /* configuration space */ + 0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x01000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, - <&clks IMX6SX_CLK_LVDS1_OUT>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LVDS1_OUT>; + clock-names = "pcie", "pcie_phy", "pcie_bus"; + pcie-supply = <®_pcie>; status = "disabled"; }; }; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index be9a51a..0a055f0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -718,6 +718,7 @@ config SOC_IMX6SL config SOC_IMX6SX bool "i.MX6 SoloX support" + select PCI_DOMAINS if PCI select PINCTRL_IMX6SX select SOC_IMX6