From patchwork Mon Sep 29 05:03:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 4993691 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F8C7BEEA6 for ; Mon, 29 Sep 2014 05:33:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 338802025B for ; Mon, 29 Sep 2014 05:33:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0F78C201BC for ; Mon, 29 Sep 2014 05:33:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751481AbaI2Fdm (ORCPT ); Mon, 29 Sep 2014 01:33:42 -0400 Received: from mail-bn1bon0140.outbound.protection.outlook.com ([157.56.111.140]:12608 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751554AbaI2FdX (ORCPT ); Mon, 29 Sep 2014 01:33:23 -0400 Received: from BN3PR0301CA0076.namprd03.prod.outlook.com (25.160.152.172) by DM2PR0301MB0862.namprd03.prod.outlook.com (25.160.215.148) with Microsoft SMTP Server (TLS) id 15.0.1039.15; Mon, 29 Sep 2014 05:33:20 +0000 Received: from BY2FFO11FD004.protection.gbl (2a01:111:f400:7c0c::177) by BN3PR0301CA0076.outlook.office365.com (2a01:111:e400:401e::44) with Microsoft SMTP Server (TLS) id 15.0.1039.15 via Frontend Transport; Mon, 29 Sep 2014 05:33:19 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD004.mail.protection.outlook.com (10.1.14.158) with Microsoft SMTP Server (TLS) id 15.0.1029.15 via Frontend Transport; Mon, 29 Sep 2014 05:33:19 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s8T5XGMl021429; Sun, 28 Sep 2014 22:33:17 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 3BED41AE20A; Mon, 29 Sep 2014 13:03:20 +0800 (CST) From: Richard Zhu To: CC: , , , , , Richard Zhu Subject: [PATCH v3 8/9] PCI: designware: refine setup_rc and add msi data restore Date: Mon, 29 Sep 2014 13:03:16 +0800 Message-ID: <1411966997-27118-9-git-send-email-r65037@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1411966997-27118-1-git-send-email-r65037@freescale.com> References: <1411966997-27118-1-git-send-email-r65037@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(81342003)(46102003)(80022003)(74502003)(81542003)(64706001)(44976005)(104166001)(101416001)(79102003)(36756003)(87936001)(33646002)(26826002)(84676001)(6806004)(74662003)(77982003)(4396001)(50466002)(50226001)(46386002)(229853001)(48376002)(99396003)(50986999)(42186005)(76176999)(77096002)(10300001)(21056001)(102836001)(19580395003)(77156001)(85306004)(87286001)(92726001)(97736003)(106466001)(92566001)(47776003)(90102001)(31966008)(2351001)(110136001)(16796002)(95666004)(89996001)(88136002)(52956003)(107046002)(19580405001)(83322001)(68736004)(120916001)(20776003)(105586002)(103686003)(45336002)(83072002)(76482002)(85852003)(62966002)(93916002)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0862; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0862; X-Forefront-PRVS: 034902F5BC Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.168.50) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - move "program correct class for RC" from dw_pcie_host_init() to dw_pcie_setup_rc(). since this is RC setup, it's better to contained in dw_pcie_setup_rc function. Then, RC can be re-setup really by dw_pcie_setup_rc(). - add one re-store msi data function. Because that pcie controller maybe powered off during system suspend, and the msi data configuration would be lost. this functions can be used to restore the msi data during the resume callback. Signed-off-by: Richard Zhu --- drivers/pci/host/pcie-designware.c | 15 ++++++++++++--- drivers/pci/host/pcie-designware.h | 1 + 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 538bbf3..ae1e6c5 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); } +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) +{ + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, + virt_to_phys((void *)pp->msi_data)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); +} + static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) { int flag = 1; @@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@ -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val = memlimit | membase; dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); + /* program correct class for RC */ + dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val); + val |= PCI_CLASS_BRIDGE_PCI << 16; + dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION); + /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index a476e60..bb75715 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); +void dw_pcie_msi_cfg_restore(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp);