From patchwork Tue Sep 30 09:36:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5001701 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3FDBBBEEA6 for ; Tue, 30 Sep 2014 10:07:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 730EF2017D for ; Tue, 30 Sep 2014 10:07:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8466C201BC for ; Tue, 30 Sep 2014 10:07:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752071AbaI3KHK (ORCPT ); Tue, 30 Sep 2014 06:07:10 -0400 Received: from mail-by2on0109.outbound.protection.outlook.com ([207.46.100.109]:28351 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751857AbaI3KHJ (ORCPT ); Tue, 30 Sep 2014 06:07:09 -0400 Received: from BY2PR03CA052.namprd03.prod.outlook.com (10.141.249.25) by BL2PR03MB338.namprd03.prod.outlook.com (10.141.68.18) with Microsoft SMTP Server (TLS) id 15.0.1044.7; Tue, 30 Sep 2014 10:07:05 +0000 Received: from BN1AFFO11FD009.protection.gbl (2a01:111:f400:7c10::118) by BY2PR03CA052.outlook.office365.com (2a01:111:e400:2c5d::25) with Microsoft SMTP Server (TLS) id 15.0.1039.15 via Frontend Transport; Tue, 30 Sep 2014 10:07:04 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD009.mail.protection.outlook.com (10.58.52.69) with Microsoft SMTP Server (TLS) id 15.0.1029.15 via Frontend Transport; Tue, 30 Sep 2014 10:07:03 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s8UA70xZ011204; Tue, 30 Sep 2014 03:07:02 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id D5B7B1AE207; Tue, 30 Sep 2014 17:36:44 +0800 (CST) From: Richard Zhu To: CC: , , , , , Richard Zhu Subject: [PATCH v4 04/10] PCI: designware: refine setup_rc and add msi data restore Date: Tue, 30 Sep 2014 17:36:38 +0800 Message-ID: <1412069804-17162-5-git-send-email-r65037@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1412069804-17162-1-git-send-email-r65037@freescale.com> References: <1412069804-17162-1-git-send-email-r65037@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(101416001)(33646002)(84676001)(229853001)(19580405001)(42186005)(120916001)(76176999)(68736004)(85852003)(110136001)(93916002)(36756003)(92566001)(102836001)(92726001)(19580395003)(87936001)(80022003)(50226001)(46102003)(44976005)(107046002)(2351001)(87286001)(6806004)(4396001)(89996001)(104166001)(52956003)(76482002)(88136002)(31966008)(21056001)(45336002)(85306004)(16796002)(46386002)(97736003)(103686003)(105586002)(95666004)(99396003)(50986999)(47776003)(77096002)(50466002)(106466001)(62966002)(10300001)(48376002)(26826002)(64706001)(77156001)(20776003)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BL2PR03MB338; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB338; X-Exchange-Antispam-Report-Test: UriScan:; X-Forefront-PRVS: 0350D7A55D Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.168.50) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - move "program correct class for RC" from dw_pcie_host_init() to dw_pcie_setup_rc(). since this is RC setup, it's better to contained in dw_pcie_setup_rc function. Then, RC can be re-setup really by dw_pcie_setup_rc(). - add one re-store msi data function. Because that pcie controller maybe powered off during system suspend, and the msi data configuration would be lost. this functions can be used to restore the msi data during the resume callback. Signed-off-by: Richard Zhu --- drivers/pci/host/pcie-designware.c | 15 ++++++++++++--- drivers/pci/host/pcie-designware.h | 1 + 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 538bbf3..ae1e6c5 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); } +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) +{ + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, + virt_to_phys((void *)pp->msi_data)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); +} + static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) { int flag = 1; @@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@ -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val = memlimit | membase; dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); + /* program correct class for RC */ + dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val); + val |= PCI_CLASS_BRIDGE_PCI << 16; + dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION); + /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index a476e60..bb75715 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); +void dw_pcie_msi_cfg_restore(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp);