From patchwork Fri Oct 10 05:15:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 5063591 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B80E3C11AC for ; Fri, 10 Oct 2014 05:15:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E2E920253 for ; Fri, 10 Oct 2014 05:15:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 156A82022D for ; Fri, 10 Oct 2014 05:15:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750990AbaJJFPz (ORCPT ); Fri, 10 Oct 2014 01:15:55 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12338 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750758AbaJJFPy (ORCPT ); Fri, 10 Oct 2014 01:15:54 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 09 Oct 2014 22:16:46 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 09 Oct 2014 22:15:39 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 09 Oct 2014 22:15:39 -0700 Received: from vidyas-desktop.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Thu, 9 Oct 2014 22:15:53 -0700 From: Vidya Sagar To: , , CC: , , , , Vidya Sagar Subject: [PATCH v2] PCI: tegra: Enable root port specific features Date: Fri, 10 Oct 2014 10:45:35 +0530 Message-ID: <1412918135-11686-1-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 1.8.1.5 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enables root port to advertise its ASPM-L1 capability resulting in possible link entry to L1 when an ASPM-L1 capable device is connected Enables per-controller & per-TMS clock clamping by default Enabling above features result in more power saving It also avoids PM message truncation by waiting for DLLP to finish before entering into L1 or L2 Signed-off-by: Vidya Sagar --- v2: Removed rp_read() & rp_write() as they seem to be redundant Moved port disable code under error condition i.e. it the link is down, corresponding port will be disabled drivers/pci/host/pci-tegra.c | 50 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 3d43874..7f32b07 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -237,6 +237,18 @@ (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ ) +#define NV_PCIE2_RP_VEND_XP1 0x00000F04 +#define NV_PCIE2_RP_VEND_XP_LINK_PVT_CTL_L1_ASPM_SUPPORT (1 << 21) + +#define NV_PCIE2_RP_VEND_XP_BIST 0x00000F4C +#define PCIE2_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) + +#define NV_PCIE2_RP_PRIV_MISC 0x00000FE0 +#define PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xF << 16) +#define PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) +#define PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xF << 24) +#define PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) + struct tegra_msi { struct msi_chip chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -1859,6 +1871,32 @@ retry: return false; } +/* Enable various features of root port */ +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) +{ + unsigned int data; + + /* Power mangagement settings */ + /* Enable clock clamping by default */ + data = readl(port->base + NV_PCIE2_RP_PRIV_MISC); + data |= PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD | + PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE | + PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD | + PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE; + writel(data, port->base + NV_PCIE2_RP_PRIV_MISC); + + /* Enable rootport to advertise its ASPM - L1 capability */ + data = readl(port->base + NV_PCIE2_RP_VEND_XP1); + data |= NV_PCIE2_RP_VEND_XP_LINK_PVT_CTL_L1_ASPM_SUPPORT; + writel(data, port->base + NV_PCIE2_RP_VEND_XP1); + + /* LTSSM : wait for DLLP to finish before entering L1 or L2/L3 */ + /* to avoid truncating PM messages resulting in receiver errors */ + data = readl(port->base + NV_PCIE2_RP_VEND_XP_BIST); + data |= PCIE2_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; + writel(data, port->base + NV_PCIE2_RP_VEND_XP_BIST); +} + static int tegra_pcie_enable(struct tegra_pcie *pcie) { struct tegra_pcie_port *port, *tmp; @@ -1870,13 +1908,15 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) tegra_pcie_port_enable(port); - if (tegra_pcie_port_check_link(port)) + if (!tegra_pcie_port_check_link(port)) { + dev_info(pcie->dev, "link %u down, ignoring\n", + port->index); + tegra_pcie_port_disable(port); + tegra_pcie_port_free(port); continue; + } - dev_info(pcie->dev, "link %u down, ignoring\n", port->index); - - tegra_pcie_port_disable(port); - tegra_pcie_port_free(port); + tegra_pcie_enable_rp_features(port); } memset(&hw, 0, sizeof(hw));