From patchwork Wed Oct 15 03:07:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 5083081 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DC8A0C11AC for ; Wed, 15 Oct 2014 02:30:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0CF7F2012F for ; Wed, 15 Oct 2014 02:30:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 241BD2012D for ; Wed, 15 Oct 2014 02:30:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756057AbaJOCaf (ORCPT ); Tue, 14 Oct 2014 22:30:35 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:56328 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932771AbaJOC0F (ORCPT ); Tue, 14 Oct 2014 22:26:05 -0400 Received: from 172.24.2.119 (EHLO szxeml412-hub.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id AVO63800; Wed, 15 Oct 2014 10:25:58 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml412-hub.china.huawei.com (10.82.67.91) with Microsoft SMTP Server id 14.3.158.1; Wed, 15 Oct 2014 10:25:50 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , , , , Arnd Bergmann , Thomas Gleixner , "Konrad Rzeszutek Wilk" , , Joerg Roedel , , , Benjamin Herrenschmidt , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Liviu Dudau , Yijing Wang Subject: [PATCH v3 20/27] MIPS/Xlr/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Wed, 15 Oct 2014 11:07:08 +0800 Message-ID: <1413342435-7876-21-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> References: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.543DDB37.004D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2a592ec8fea66c42bba217ed0721ce4c Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/mips/pci/pci-xlr.c | 17 +++++++++++++++-- 1 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 0dde803..0e611de 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -149,6 +149,8 @@ static struct resource nlm_pci_io_resource = { .flags = IORESOURCE_IO, }; +static struct msi_chip xlr_msi_chip; + struct pci_controller nlm_pci_controller = { .index = 0, .pci_ops = &nlm_pci_ops, @@ -156,6 +158,9 @@ struct pci_controller nlm_pci_controller = { .mem_offset = 0x00000000UL, .io_resource = &nlm_pci_io_resource, .io_offset = 0x00000000UL, +#ifdef CONFIG_PCI_MSI + .msi_chip = &xlr_msi_chip, +#endif }; /* @@ -214,11 +219,13 @@ static int get_irq_vector(const struct pci_dev *dev) } #ifdef CONFIG_PCI_MSI -void arch_teardown_msi_irq(unsigned int irq) +static void xlr_teardown_msi_irq(struct msi_chip *chip, + unsigned int irq) { } -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) +static int xlr_setup_msi_irq(struct msi_chip *chip, + struct pci_dev *dev, struct msi_desc *desc) { struct msi_msg msg; struct pci_dev *lnk; @@ -263,6 +270,12 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) write_msi_msg(irq, &msg); return 0; } + +static struct msi_chip xlr_msi_chip = { + .setup_irq = xlr_setup_msi_irq, + .teardown_irq = xlr_teardown_msi_irq, +}; + #endif /* Extra ACK needed for XLR on chip PCI controller */