From patchwork Mon Oct 20 02:19:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5101911 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EFE379F30B for ; Mon, 20 Oct 2014 02:51:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2EDE201B9 for ; Mon, 20 Oct 2014 02:51:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CBEF5201F2 for ; Mon, 20 Oct 2014 02:51:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752037AbaJTCvh (ORCPT ); Sun, 19 Oct 2014 22:51:37 -0400 Received: from [207.46.100.106] ([207.46.100.106]:8224 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752008AbaJTCvd (ORCPT ); Sun, 19 Oct 2014 22:51:33 -0400 Received: from BN3PR0301CA0056.namprd03.prod.outlook.com (25.160.152.152) by BY1PR0301MB0855.namprd03.prod.outlook.com (25.160.193.149) with Microsoft SMTP Server (TLS) id 15.0.1054.13; Mon, 20 Oct 2014 02:49:41 +0000 Received: from BN1BFFO11FD038.protection.gbl (2a01:111:f400:7c10::1:188) by BN3PR0301CA0056.outlook.office365.com (2a01:111:e400:401e::24) with Microsoft SMTP Server (TLS) id 15.0.1054.13 via Frontend Transport; Mon, 20 Oct 2014 02:49:40 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD038.mail.protection.outlook.com (10.58.144.101) with Microsoft SMTP Server (TLS) id 15.0.1049.20 via Frontend Transport; Mon, 20 Oct 2014 02:49:39 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9K2nZtq019779; Sun, 19 Oct 2014 19:49:38 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 214D81AE214; Mon, 20 Oct 2014 10:19:18 +0800 (CST) From: Richard Zhu To: CC: , , , , Richard Zhu , Richard Zhu Subject: [PATCH v7 11/13] ARM: imx6: Update dts and binding for imx6sx pcie Date: Mon, 20 Oct 2014 10:19:14 +0800 Message-ID: <1413771556-32212-12-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1413771556-32212-1-git-send-email-richard.zhu@freescale.com> References: <1413771556-32212-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(85852003)(16796002)(31966008)(88136002)(44976005)(19580395003)(6806004)(68736004)(87936001)(69596002)(19580405001)(52956003)(89996001)(84676001)(87286001)(110136001)(80022003)(46102003)(33646002)(47776003)(20776003)(4396001)(64706001)(95666004)(76482002)(103686003)(229853001)(2351001)(107046002)(105586002)(81156004)(106466001)(99396003)(97736003)(120916001)(26826002)(102836001)(101416001)(76176999)(50986999)(50466002)(48376002)(93916002)(92566001)(92726001)(77096002)(50226001)(85306004)(21056001)(42186005)(104166001)(62966002)(45336002)(77156001)(36756003)(46386002)(32563001)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR0301MB0855; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:0; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB0855; X-Forefront-PRVS: 03706074BC Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Zhu - imx6sx pcie phy has its own power regulator. Add the pcie phy power suppy into im6sx pcie dts and binding. - in order to align with imx6qdl's pcie dts, re-format imx6sx pcie dts. - in order to align with imx6qdl pcie dts format and keep clean of imx6 pcie driver, keep the pcie phy clock in imx6sx pcie dts, although it's the parent clk of the pcie bus clock now, and would be enabled automatically when pcie bus clock is enabled. secondly, it's possible that the external osc maybe used as source of the pcie_bus clk in board design in future. - disp_axi clock is required by pcie inbound axi port. Add one more clock named pcie_inbound_axi for imx6sx pcie. Signed-off-by: Richard Zhu --- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 8 +++++- arch/arm/boot/dts/imx6sx.dtsi | 32 ++++++++++++---------- 2 files changed, 25 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 9455fd0..ad81179 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "fsl,imx6q-pcie" +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie" - reg: base addresse and length of the pcie controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -13,6 +13,12 @@ Required properties: - clock-names: Must include the following additional entries: - "pcie_phy" +Additional required properties for imx6sx-pcie: +- clock names: Must include the following additional entries: + - "pcie_inbound_axi" +- power supplies: + - pcie-phy-supply: regulator used to power the PCIe PHY + Example: pcie@0x01000000 { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index f4b9da6..0dfeade 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -599,9 +599,9 @@ anatop-max-voltage = <1450000>; }; - reg_pcie: regulator-vddpcie@140 { + reg_pcie_phy: regulator-vddpcie-phy@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; + regulator-name = "vddpcie-phy"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; anatop-reg-offset = <0x140>; @@ -1184,24 +1184,28 @@ pcie: pcie@0x08000000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x4000>; /* DBI */ + reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 - /* downstream I/O */ - 0x81000000 0 0 0x08f80000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + pcie-phy-supply = <®_pcie_phy>; status = "disabled"; }; };