From patchwork Mon Oct 20 05:25:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5102611 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3CE229FAC5 for ; Mon, 20 Oct 2014 05:55:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 38A5520179 for ; Mon, 20 Oct 2014 05:55:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 30EA32020F for ; Mon, 20 Oct 2014 05:55:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752484AbaJTFzu (ORCPT ); Mon, 20 Oct 2014 01:55:50 -0400 Received: from mail-by2on0143.outbound.protection.outlook.com ([207.46.100.143]:2656 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752485AbaJTFzr (ORCPT ); Mon, 20 Oct 2014 01:55:47 -0400 Received: from BY2PR03CA002.namprd03.prod.outlook.com (10.255.93.19) by BY1PR0301MB0856.namprd03.prod.outlook.com (25.160.193.15) with Microsoft SMTP Server (TLS) id 15.0.1054.13; Mon, 20 Oct 2014 05:55:44 +0000 Received: from BN1AFFO11FD024.protection.gbl (10.255.93.4) by BY2PR03CA002.outlook.office365.com (10.255.93.19) with Microsoft SMTP Server (TLS) id 15.0.1054.13 via Frontend Transport; Mon, 20 Oct 2014 05:55:44 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD024.mail.protection.outlook.com (10.58.52.84) with Microsoft SMTP Server (TLS) id 15.0.1049.20 via Frontend Transport; Mon, 20 Oct 2014 05:55:44 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9K5tbqK017257; Sun, 19 Oct 2014 22:55:38 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 6B2441AE209; Mon, 20 Oct 2014 13:25:25 +0800 (CST) From: Richard Zhu To: CC: , , , , , Richard Zhu , Richard Zhu Subject: [PATCH v8 1/9] PCI: designware: Refine setup_rc and add msi data restore Date: Mon, 20 Oct 2014 13:25:16 +0800 Message-ID: <1413782724-30795-2-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1413782724-30795-1-git-send-email-richard.zhu@freescale.com> References: <1413782724-30795-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(50226001)(31966008)(42186005)(4396001)(46386002)(64706001)(16796002)(20776003)(45336002)(47776003)(95666004)(103686003)(105586002)(229853001)(2351001)(107046002)(81156004)(106466001)(62966002)(104166001)(50466002)(48376002)(77096002)(33646002)(110136001)(6806004)(44976005)(52956003)(89996001)(85852003)(87286001)(88136002)(87936001)(85306004)(76176999)(19580405001)(19580395003)(68736004)(69596002)(84676001)(50986999)(21056001)(26826002)(76482002)(92566001)(102836001)(92726001)(80022003)(46102003)(93916002)(99396003)(101416001)(120916001)(36756003)(97736003)(77156001)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR0301MB0856; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB0856; X-Forefront-PRVS: 03706074BC Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Zhu - move "program correct class for RC" from dw_pcie_host_init() to dw_pcie_setup_rc(). since this is RC setup, it's better to contained in dw_pcie_setup_rc function. Then, RC can be re-setup really by dw_pcie_setup_rc(). - add one store/re-store msi cfg functions. Because that pcie controller maybe powered off during system suspend, and the msi data configuration would be lost. these functions can be used to store/restore the msi data and msi_enable during the suspend/resume callback. * all the four msi enable register are stored/re-stored. * use pp->ops->get_msi_data if there is get_msi_data callback. Signed-off-by: Richard Zhu --- drivers/pci/host/pcie-designware.c | 41 +++++++++++++++++++++++++++++++++++--- drivers/pci/host/pcie-designware.h | 6 ++++++ 2 files changed, 44 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 538bbf3..8d1c809 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -44,6 +44,15 @@ #define PCIE_MSI_INTR0_ENABLE 0x828 #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_MSI_INTR1_ENABLE 0x834 +#define PCIE_MSI_INTR1_MASK 0x838 +#define PCIE_MSI_INTR1_STATUS 0x83C +#define PCIE_MSI_INTR2_ENABLE 0x840 +#define PCIE_MSI_INTR2_MASK 0x844 +#define PCIE_MSI_INTR2_STATUS 0x848 +#define PCIE_MSI_INTR3_ENABLE 0x84C +#define PCIE_MSI_INTR3_MASK 0x850 +#define PCIE_MSI_INTR3_STATUS 0x854 #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) @@ -194,6 +203,32 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); } +void dw_pcie_msi_cfg_store(struct pcie_port *pp) +{ + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &pp->msi_int0_enable); + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR1_ENABLE, 4, &pp->msi_int1_enable); + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR2_ENABLE, 4, &pp->msi_int2_enable); + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR3_ENABLE, 4, &pp->msi_int3_enable); +} + +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) +{ + u32 address_lo; + + if (pp->ops->get_msi_data) + address_lo = pp->ops->get_msi_data(pp); + else + address_lo = virt_to_phys((void *)pp->msi_data); + + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, address_lo); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); + + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, pp->msi_int0_enable); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR1_ENABLE, 4, pp->msi_int1_enable); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR2_ENABLE, 4, pp->msi_int2_enable); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR3_ENABLE, 4, pp->msi_int3_enable); +} + static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) { int flag = 1; @@ -570,9 +605,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@ -917,6 +949,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val = memlimit | membase; dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); + /* program correct class for RC */ + dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index a476e60..1a59600 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -56,6 +56,10 @@ struct pcie_port { int msi_irq; struct irq_domain *irq_domain; unsigned long msi_data; + unsigned int msi_int0_enable; + unsigned int msi_int1_enable; + unsigned int msi_int2_enable; + unsigned int msi_int3_enable; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); }; @@ -83,6 +87,8 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); +void dw_pcie_msi_cfg_store(struct pcie_port *pp); +void dw_pcie_msi_cfg_restore(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp);