From patchwork Mon Oct 27 05:17:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5157361 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0E43F9F318 for ; Mon, 27 Oct 2014 05:48:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8288C202F0 for ; Mon, 27 Oct 2014 05:48:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F47420176 for ; Mon, 27 Oct 2014 05:48:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751739AbaJ0Fsb (ORCPT ); Mon, 27 Oct 2014 01:48:31 -0400 Received: from mail-bl2on0115.outbound.protection.outlook.com ([65.55.169.115]:53482 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752356AbaJ0Frs (ORCPT ); Mon, 27 Oct 2014 01:47:48 -0400 Received: from DM2PR03CA0022.namprd03.prod.outlook.com (10.141.96.21) by BY1PR0301MB0856.namprd03.prod.outlook.com (25.160.193.15) with Microsoft SMTP Server (TLS) id 15.1.6.9; Mon, 27 Oct 2014 05:47:44 +0000 Received: from BL2FFO11FD052.protection.gbl (2a01:111:f400:7c09::136) by DM2PR03CA0022.outlook.office365.com (2a01:111:e400:2428::21) with Microsoft SMTP Server (TLS) id 15.1.6.9 via Frontend Transport; Mon, 27 Oct 2014 05:47:44 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD052.mail.protection.outlook.com (10.173.161.214) with Microsoft SMTP Server (TLS) id 15.0.1049.20 via Frontend Transport; Mon, 27 Oct 2014 05:47:43 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s9R5lebf030626; Sun, 26 Oct 2014 22:47:41 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id E73D11AE20B; Mon, 27 Oct 2014 13:17:33 +0800 (CST) From: Richard Zhu To: CC: , , , , , , Richard Zhu , Richard Zhu Subject: [PATCH V3] PCI: imx6: Wait the clocks to stabilize after ref_en Date: Mon, 27 Oct 2014 13:17:32 +0800 Message-ID: <1414387052-3582-2-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1414387052-3582-1-git-send-email-richard.zhu@freescale.com> References: <1414387052-3582-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(19580395003)(68736004)(77096002)(99396003)(46386002)(76482002)(85852003)(52956003)(48376002)(92726001)(6806004)(104166001)(80022003)(2351001)(46102003)(50466002)(89996001)(47776003)(42186005)(4396001)(20776003)(84676001)(92566001)(77156001)(36756003)(19580405001)(44976005)(101416001)(102836001)(93916002)(88136002)(85306004)(45336002)(50226001)(26826002)(107046002)(106466001)(229853001)(87936001)(50986999)(76176999)(21056001)(110136001)(105586002)(97736003)(87286001)(33646002)(95666004)(64706001)(62966002)(103686003)(120916001)(31966008)(16796002)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR0301MB0856; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:0; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB0856; X-Forefront-PRVS: 0377802854 Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.168.50) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Zhu For boards without a reset GPIO we skip the delay between enabling the pcie_ref_clk and touching the RC registers for configuration. This hangs the system if there isn't a proper delay to ensure the clocks are settled in the DW PCIe core. Also iMX6Q always needs an additional 10us delay to make sure the reset is propagated through the core, as we don't have an explicitly controlled reset input on this SoC. Signed-off-by: Richard Zhu Tested-by: Fabio Estevam Acked-by: Lucas Stach --- drivers/pci/host/pci-imx6.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 233fe8a..eac96fb 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); - /* power up core phy and enable ref clock */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + /* + * the async reset input need ref clock to sync internally, + * when the ref clock comes after reset, internal synced + * reset time is too short , cannot meet the requirement. + * add one ~10us delay here. + */ + udelay(10); regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* allow the clocks to stabilize */ + usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);