From patchwork Mon Oct 27 13:22:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 5160261 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 33D849F318 for ; Mon, 27 Oct 2014 12:44:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 51811202F8 for ; Mon, 27 Oct 2014 12:44:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6BB5D20254 for ; Mon, 27 Oct 2014 12:44:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752562AbaJ0Ml7 (ORCPT ); Mon, 27 Oct 2014 08:41:59 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:28075 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752446AbaJ0Mlm (ORCPT ); Mon, 27 Oct 2014 08:41:42 -0400 Received: from 172.24.2.119 (EHLO szxeml404-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CBJ49240; Mon, 27 Oct 2014 20:41:34 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml404-hub.china.huawei.com (10.82.67.59) with Microsoft SMTP Server id 14.3.158.1; Mon, 27 Oct 2014 20:41:26 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , Thomas Gleixner , Konrad Rzeszutek Wilk , , Joerg Roedel , , , "Benjamin Herrenschmidt" , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Yijing Wang Subject: [PATCH 09/16] MIPS/Xlr/MSI: Use MSI controller framework to configure MSI/MSI-X irq Date: Mon, 27 Oct 2014 21:22:15 +0800 Message-ID: <1414416142-31239-10-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> References: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use MSI controller framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/mips/pci/pci-xlr.c | 17 +++++++++++++++-- 1 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 0dde803..1e43c70 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -149,6 +149,8 @@ static struct resource nlm_pci_io_resource = { .flags = IORESOURCE_IO, }; +static struct msi_controller xlr_msi_ctrl; + struct pci_controller nlm_pci_controller = { .index = 0, .pci_ops = &nlm_pci_ops, @@ -156,6 +158,9 @@ struct pci_controller nlm_pci_controller = { .mem_offset = 0x00000000UL, .io_resource = &nlm_pci_io_resource, .io_offset = 0x00000000UL, +#ifdef CONFIG_PCI_MSI + .msi_ctrl = &xlr_msi_ctrl, +#endif }; /* @@ -214,11 +219,13 @@ static int get_irq_vector(const struct pci_dev *dev) } #ifdef CONFIG_PCI_MSI -void arch_teardown_msi_irq(unsigned int irq) +static void xlr_teardown_msi_irq(struct msi_controller *ctrl, + unsigned int irq) { } -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) +static int xlr_setup_msi_irq(struct msi_controller *ctrl, + struct pci_dev *dev, struct msi_desc *desc) { struct msi_msg msg; struct pci_dev *lnk; @@ -263,6 +270,12 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) write_msi_msg(irq, &msg); return 0; } + +static struct msi_controller xlr_msi_ctrl = { + .setup_irq = xlr_setup_msi_irq, + .teardown_irq = xlr_teardown_msi_irq, +}; + #endif /* Extra ACK needed for XLR on chip PCI controller */