From patchwork Mon Oct 27 13:22:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 5160251 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 66D76C11AC for ; Mon, 27 Oct 2014 12:44:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 646132035B for ; Mon, 27 Oct 2014 12:44:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72A1D20254 for ; Mon, 27 Oct 2014 12:44:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752990AbaJ0MmA (ORCPT ); Mon, 27 Oct 2014 08:42:00 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:28141 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752625AbaJ0Mlm (ORCPT ); Mon, 27 Oct 2014 08:41:42 -0400 Received: from 172.24.2.119 (EHLO szxeml404-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CBJ49246; Mon, 27 Oct 2014 20:41:39 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml404-hub.china.huawei.com (10.82.67.59) with Microsoft SMTP Server id 14.3.158.1; Mon, 27 Oct 2014 20:41:32 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , Thomas Gleixner , Konrad Rzeszutek Wilk , , Joerg Roedel , , , "Benjamin Herrenschmidt" , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Yijing Wang Subject: [PATCH 13/16] IA64/MSI: Use MSI controller framework to configure MSI/MSI-X irq Date: Mon, 27 Oct 2014 21:22:19 +0800 Message-ID: <1414416142-31239-14-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> References: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use MSI controller framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/ia64/include/asm/pci.h | 3 ++- arch/ia64/kernel/msi_ia64.c | 24 ++++++++++++++++++------ arch/ia64/pci/pci.c | 1 + 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h index 52af5ed..805bbc3 100644 --- a/arch/ia64/include/asm/pci.h +++ b/arch/ia64/include/asm/pci.h @@ -93,7 +93,7 @@ struct pci_controller { void *iommu; int segment; int node; /* nearest node with memory or NUMA_NO_NODE for global allocation */ - + struct msi_controller *msi_ctrl; void *platform_data; }; @@ -101,6 +101,7 @@ struct pci_controller { #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata) #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment) +extern struct msi_controller ia64_msi_ctrl; extern struct pci_ops pci_root_ops; static inline int pci_proc_domain(struct pci_bus *bus) diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c index 8c3730c..b92b8e2 100644 --- a/arch/ia64/kernel/msi_ia64.c +++ b/arch/ia64/kernel/msi_ia64.c @@ -42,7 +42,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata, } #endif /* CONFIG_SMP */ -int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +int __ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) { struct msi_msg msg; unsigned long dest_phys_id; @@ -77,7 +77,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) return 0; } -void ia64_teardown_msi_irq(unsigned int irq) +void __ia64_teardown_msi_irq(unsigned int irq) { destroy_irq(irq); } @@ -111,23 +111,35 @@ static struct irq_chip ia64_msi_chip = { .irq_retrigger = ia64_msi_retrigger_irq, }; +struct msi_controller *pcibios_msi_controller(struct pci_bus *bus) +{ + struct pci_controller *ctrl = bus->sysdata; + + return ctrl->msi_ctrl; +} -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +static int ia64_setup_msi_irq(struct msi_controller *ctrl, + struct pci_dev *pdev, struct msi_desc *desc) { if (platform_setup_msi_irq) return platform_setup_msi_irq(pdev, desc); - return ia64_setup_msi_irq(pdev, desc); + return __ia64_setup_msi_irq(pdev, desc); } -void arch_teardown_msi_irq(unsigned int irq) +static void ia64_teardown_msi_irq(struct msi_controller *ctrl, unsigned int irq) { if (platform_teardown_msi_irq) return platform_teardown_msi_irq(irq); - return ia64_teardown_msi_irq(irq); + return __ia64_teardown_msi_irq(irq); } +struct msi_controller ia64_msi_ctrl = { + .setup_irq = ia64_setup_msi_irq, + .teardown_irq = ia64_teardown_msi_irq, +}; + #ifdef CONFIG_INTEL_IOMMU #ifdef CONFIG_SMP static int dmar_msi_set_affinity(struct irq_data *data, diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 291a582..875f46a 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -437,6 +437,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) controller->companion = device; controller->node = acpi_get_node(device->handle); + controller->msi_ctrl = &ia64_msi_ctrl; info = kzalloc(sizeof(*info), GFP_KERNEL); if (!info) {