From patchwork Tue Oct 28 11:54:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 5176111 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BDF159F3ED for ; Tue, 28 Oct 2014 11:59:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E54CC2024F for ; Tue, 28 Oct 2014 11:59:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 03ADD201F2 for ; Tue, 28 Oct 2014 11:59:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755390AbaJ1L4q (ORCPT ); Tue, 28 Oct 2014 07:56:46 -0400 Received: from mail-bn1bon0119.outbound.protection.outlook.com ([157.56.111.119]:55646 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755346AbaJ1L4m (ORCPT ); Tue, 28 Oct 2014 07:56:42 -0400 Received: from BN1PR02CA0029.namprd02.prod.outlook.com (10.141.56.29) by BN1PR02MB198.namprd02.prod.outlook.com (10.242.214.151) with Microsoft SMTP Server (TLS) id 15.1.6.9; Tue, 28 Oct 2014 11:56:35 +0000 Received: from BY2FFO11FD054.protection.gbl (2a01:111:f400:7c0c::172) by BN1PR02CA0029.outlook.office365.com (2a01:111:e400:2a::29) with Microsoft SMTP Server (TLS) id 15.1.6.9 via Frontend Transport; Tue, 28 Oct 2014 11:56:35 +0000 Received: from atltwp01.amd.com (165.204.84.221) by BY2FFO11FD054.mail.protection.outlook.com (10.1.15.191) with Microsoft SMTP Server id 15.0.1049.20 via Frontend Transport; Tue, 28 Oct 2014 11:56:34 +0000 X-WSS-ID: 0NE5L67-07-BGL-02 X-M-MSG: Received: from satlvexedge01.amd.com (satlvexedge01.amd.com [10.177.96.28]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.3.1) with ESMTPS id 265ABCAE644; Tue, 28 Oct 2014 06:56:31 -0500 (CDT) Received: from SATLEXDAG02.amd.com (10.181.40.5) by satlvexedge01.amd.com (10.177.96.28) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 28 Oct 2014 06:56:45 -0500 Received: from SCYBEXDAG02.amd.com (10.34.11.12) by SATLEXDAG02.amd.com (10.181.40.5) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 28 Oct 2014 07:56:32 -0400 Received: from hr-ub.amd.com (10.237.75.143) by SCYBEXDAG02.amd.com (10.34.11.12) with Microsoft SMTP Server id 14.3.195.1; Tue, 28 Oct 2014 19:56:28 +0800 From: Huang Rui To: Felipe Balbi , Alan Stern , "Bjorn Helgaas" , Greg Kroah-Hartman CC: Paul Zimmerman , Heikki Krogerus , Jason Chang , "Vincent Wan" , Tony Li , , , , Huang Rui Subject: [PATCH v3 10/19] usb: dwc3: add delay phy power change quirk Date: Tue, 28 Oct 2014 19:54:31 +0800 Message-ID: <1414497280-3126-11-git-send-email-ray.huang@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1414497280-3126-1-git-send-email-ray.huang@amd.com> References: <1414497280-3126-1-git-send-email-ray.huang@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(979002)(6009001)(428002)(199003)(189002)(85852003)(2171001)(84676001)(106466001)(80022003)(48376002)(46102003)(33646002)(87936001)(105586002)(50466002)(76176999)(50986999)(92566001)(92726001)(101416001)(575784001)(86362001)(120916001)(93916002)(31966008)(19580405001)(44976005)(95666004)(62966002)(99396003)(21056001)(4396001)(76482002)(87286001)(50226001)(102836001)(97736003)(64706001)(19580395003)(77096002)(88136002)(85306004)(68736004)(47776003)(77156001)(20776003)(107046002)(89996001)(36756003)(53416004)(104166001)(229853001)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN1PR02MB198; H:atltwp01.amd.com; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BN1PR02MB198; X-Forefront-PRVS: 0378F1E47A Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=Ray.Huang@amd.com; X-OriginatorOrg: amd4.onmicrosoft.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively, and some special platforms can configure that if it is needed. Signed-off-by: Huang Rui --- drivers/usb/dwc3/core.c | 6 ++++++ drivers/usb/dwc3/core.h | 3 +++ drivers/usb/dwc3/platform_data.h | 1 + 3 files changed, 10 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 244c71a..97796d7 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -383,6 +383,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc) if (dwc->del_p1p2p3_quirk) reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; + if (dwc->del_phy_power_chg_quirk) + reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); mdelay(100); @@ -761,6 +764,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,req_p1p2p3_quirk"); dwc->del_p1p2p3_quirk = of_property_read_bool(node, "snps,del_p1p2p3_quirk"); + dwc->del_phy_power_chg_quirk = of_property_read_bool(node, + "snps,del_phy_power_chg_quirk"); } else if (pdata) { dwc->maximum_speed = pdata->maximum_speed; dwc->has_lpm_erratum = pdata->has_lpm_erratum; @@ -775,6 +780,7 @@ static int dwc3_probe(struct platform_device *pdev) dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; + dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; } /* default to superspeed if no maximum_speed passed */ diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index a91f42d..13bc46b 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -181,6 +181,7 @@ #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) +#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) /* Global TX Fifo Size Register */ @@ -689,6 +690,7 @@ struct dwc3_scratchpad_array { * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk + * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk */ struct dwc3 { struct usb_ctrlrequest *ctrl_req; @@ -801,6 +803,7 @@ struct dwc3 { unsigned u2ss_inp3_quirk:1; unsigned req_p1p2p3_quirk:1; unsigned del_p1p2p3_quirk:1; + unsigned del_phy_power_chg_quirk:1; }; /* -------------------------------------------------------------------------- */ diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h index 6dca665..1dea0c0 100644 --- a/drivers/usb/dwc3/platform_data.h +++ b/drivers/usb/dwc3/platform_data.h @@ -32,4 +32,5 @@ struct dwc3_platform_data { unsigned u2ss_inp3_quirk:1; unsigned req_p1p2p3_quirk:1; unsigned del_p1p2p3_quirk:1; + unsigned del_phy_power_chg_quirk:1; };