From patchwork Tue Oct 28 11:54:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 5176141 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7DACC9F818 for ; Tue, 28 Oct 2014 12:00:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 630B820172 for ; Tue, 28 Oct 2014 12:00:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7760020211 for ; Tue, 28 Oct 2014 12:00:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755317AbaJ1L4a (ORCPT ); Tue, 28 Oct 2014 07:56:30 -0400 Received: from mail-bl2on0129.outbound.protection.outlook.com ([65.55.169.129]:48576 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755031AbaJ1L4Z (ORCPT ); Tue, 28 Oct 2014 07:56:25 -0400 Received: from BY1PR0201CA0031.namprd02.prod.outlook.com (25.160.191.169) by BN1PR02MB199.namprd02.prod.outlook.com (10.242.214.154) with Microsoft SMTP Server (TLS) id 15.1.6.9; Tue, 28 Oct 2014 11:56:21 +0000 Received: from BN1BFFO11FD052.protection.gbl (2a01:111:f400:7c10::1:168) by BY1PR0201CA0031.outlook.office365.com (2a01:111:e400:4814::41) with Microsoft SMTP Server (TLS) id 15.1.6.9 via Frontend Transport; Tue, 28 Oct 2014 11:56:20 +0000 Received: from atltwp01.amd.com (165.204.84.221) by BN1BFFO11FD052.mail.protection.outlook.com (10.58.145.7) with Microsoft SMTP Server id 15.0.1049.20 via Frontend Transport; Tue, 28 Oct 2014 11:56:19 +0000 X-WSS-ID: 0NE5L5T-07-BGC-02 X-M-MSG: Received: from satlvexedge02.amd.com (satlvexedge02.amd.com [10.177.96.29]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.3.1) with ESMTPS id 2BC62CAE61D; Tue, 28 Oct 2014 06:56:16 -0500 (CDT) Received: from SATLEXDAG02.amd.com (10.181.40.5) by SATLVEXEDGE02.amd.com (10.177.96.29) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 28 Oct 2014 06:56:31 -0500 Received: from SCYBEXDAG02.amd.com (10.34.11.12) by SATLEXDAG02.amd.com (10.181.40.5) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 28 Oct 2014 07:56:17 -0400 Received: from hr-ub.amd.com (10.237.75.143) by SCYBEXDAG02.amd.com (10.34.11.12) with Microsoft SMTP Server id 14.3.195.1; Tue, 28 Oct 2014 19:56:15 +0800 From: Huang Rui To: Felipe Balbi , Alan Stern , "Bjorn Helgaas" , Greg Kroah-Hartman CC: Paul Zimmerman , Heikki Krogerus , Jason Chang , "Vincent Wan" , Tony Li , , , , Huang Rui Subject: [PATCH v3 07/19] usb: dwc3: add P3 in U2 SS inactive quirk Date: Tue, 28 Oct 2014 19:54:28 +0800 Message-ID: <1414497280-3126-8-git-send-email-ray.huang@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1414497280-3126-1-git-send-email-ray.huang@amd.com> References: <1414497280-3126-1-git-send-email-ray.huang@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(46102003)(80022003)(92726001)(85306004)(31966008)(92566001)(87936001)(48376002)(2171001)(88136002)(85852003)(89996001)(102836001)(229853001)(106466001)(76176999)(50986999)(101416001)(107046002)(97736003)(93916002)(86362001)(104166001)(95666004)(19580405001)(105586002)(19580395003)(76482002)(77156001)(68736004)(4396001)(50226001)(33646002)(21056001)(36756003)(77096002)(120916001)(62966002)(87286001)(44976005)(50466002)(53416004)(84676001)(47776003)(20776003)(64706001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN1PR02MB199; H:atltwp01.amd.com; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BN1PR02MB199; X-Forefront-PRVS: 0378F1E47A Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=Ray.Huang@amd.com; X-OriginatorOrg: amd4.onmicrosoft.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds P3 in U2 SS inactive quirk, and some special platforms can configure that if it is needed. Signed-off-by: Huang Rui --- drivers/usb/dwc3/core.c | 23 +++++++++++++++++++++++ drivers/usb/dwc3/core.h | 3 +++ drivers/usb/dwc3/platform_data.h | 1 + 3 files changed, 27 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 6abf4e9..ccc54df 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -365,6 +365,24 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) } /** + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core + * @dwc: Pointer to our controller context structure + */ +static void dwc3_phy_setup(struct dwc3 *dwc) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + + if (dwc->u2ss_inp3_quirk) + reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; + + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + + mdelay(100); +} + +/** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure * @@ -484,6 +502,8 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_phy_setup(dwc); + ret = dwc3_alloc_scratch_buffers(dwc); if (ret) goto err1; @@ -729,6 +749,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,disable_scramble_quirk"); dwc->u2exit_lfps_quirk = of_property_read_bool(node, "snps,u2exit_lfps_quirk"); + dwc->u2ss_inp3_quirk = of_property_read_bool(node, + "snps,u2ss_inp3_quirk"); } else if (pdata) { dwc->maximum_speed = pdata->maximum_speed; dwc->has_lpm_erratum = pdata->has_lpm_erratum; @@ -740,6 +762,7 @@ static int dwc3_probe(struct platform_device *pdev) dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; + dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; } /* default to superspeed if no maximum_speed passed */ diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 03e0505..f230668 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -176,6 +176,7 @@ /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) +#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) /* Global TX Fifo Size Register */ @@ -681,6 +682,7 @@ struct dwc3_scratchpad_array { * @three_stage_setup: set if we perform a three phase setup * @disable_scramble_quirk: set if we enable the disable scramble quirk * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk + * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk */ struct dwc3 { struct usb_ctrlrequest *ctrl_req; @@ -790,6 +792,7 @@ struct dwc3 { unsigned disable_scramble_quirk:1; unsigned u2exit_lfps_quirk:1; + unsigned u2ss_inp3_quirk:1; }; /* -------------------------------------------------------------------------- */ diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h index 4e91e09..b5906a3 100644 --- a/drivers/usb/dwc3/platform_data.h +++ b/drivers/usb/dwc3/platform_data.h @@ -29,4 +29,5 @@ struct dwc3_platform_data { unsigned has_lpm_erratum:1; unsigned lpm_nyet_thres:4; unsigned u2exit_lfps_quirk:1; + unsigned u2ss_inp3_quirk:1; };