From patchwork Fri Dec 12 17:13:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 5484241 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7F96ABEEA8 for ; Fri, 12 Dec 2014 17:17:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5963B201EF for ; Fri, 12 Dec 2014 17:17:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D092920103 for ; Fri, 12 Dec 2014 17:17:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031030AbaLLRRJ (ORCPT ); Fri, 12 Dec 2014 12:17:09 -0500 Received: from ns.mm-sol.com ([37.157.136.199]:33635 "EHLO extserv.mm-sol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030596AbaLLRRI (ORCPT ); Fri, 12 Dec 2014 12:17:08 -0500 Received: from localhost.localdomain (unknown [37.157.136.206]) by extserv.mm-sol.com (Postfix) with ESMTPSA id ADCFDC83F; Fri, 12 Dec 2014 19:17:06 +0200 (EET) From: Stanimir Varbanov To: Rob Herring , Kumar Gala , Mark Rutland , Grant Likely , Bjorn Helgaas , Kishon Vijay Abraham I , Russell King , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Stanimir Varbanov Subject: [PATCH 1/5] DT: phy: qcom: Add PCIe PHY devicetree bindings Date: Fri, 12 Dec 2014 19:13:57 +0200 Message-Id: <1418404441-5518-2-git-send-email-svarbanov@mm-sol.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1418404441-5518-1-git-send-email-svarbanov@mm-sol.com> References: <1418404441-5518-1-git-send-email-svarbanov@mm-sol.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document Qualcomm PCIe PHY devicetree bindings. Signed-off-by: Stanimir Varbanov --- .../devicetree/bindings/phy/qcom-pcie-phy.txt | 62 ++++++++++++++++++++ 1 files changed, 62 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt new file mode 100644 index 0000000..f53eaf3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt @@ -0,0 +1,62 @@ +* Qualcomm PCIe PHY controller + +PCIe PHY nodes are defined to describe on-chip SATA Physical layer controllers. +Each SATA PHY controller should have its own node. + +- compatible: + Usage: required + Value type: + Definition: Value should contain "qcom,pcie-phy" + +- reg: + Usage: required + Value type: + Definition: Offset and length of the PCIe PHY registers + +- #phy-cells: + Usage: required + Value type: + Definition: Must be zero + +- clocks: + Usage: required + Value type: + Definition: A list of phandles and clock specifier pair, one + for each entry in clock-names property + +- clock-names: + Usage: required + Value type: + Definition: Must be "core" for PHY core clock + +- resets: + Usage: required + Value type: + Definition: List of phandle and reset specifier pairs as listed + in reset-names property + +- reset-names: + Usage: required + Value type: + Definition: Should contain "phy" for PHY reset + +- -supply: + Usage: required + Value type: + Definition: List of phandles to the supply regulators + - "vdda" analog Vdd supply + - "vdda_pll" analog Vdd PLL supply + +* Example + + pciephy0: phy@fc526000 { + compatible = "qcom,pcie-phy"; + reg = <0xfc526000 0x1000>; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "core"; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + vdda-supply = <&pma8084_l3>; + vdda_pll-supply = <&pma8084_l12>; + #phy-cells = <0>; + };