From patchwork Tue Mar 10 11:35:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 5976641 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5BCFCBF440 for ; Tue, 10 Mar 2015 11:37:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B8708201BC for ; Tue, 10 Mar 2015 11:37:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D418B20154 for ; Tue, 10 Mar 2015 11:37:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752772AbbCJLh0 (ORCPT ); Tue, 10 Mar 2015 07:37:26 -0400 Received: from mail-la0-f41.google.com ([209.85.215.41]:36838 "EHLO mail-la0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752765AbbCJLeh (ORCPT ); Tue, 10 Mar 2015 07:34:37 -0400 Received: by labgd6 with SMTP id gd6so982788lab.3 for ; Tue, 10 Mar 2015 04:34:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XubwWYOsv3Nxc7e+lrSYN1gukLOM4gdx/jBhbo4T9uw=; b=Bk7f1TrVbDOXX0U9a34nEC/k1NBpCxNUSgzRBrk4C5xcDPW43zV9cOL9xcLTJyxoON 7Hiaax1sN5jkf+vI25olRv7Wq626k6xDRsZ4dlm4mAuPJWbwU3Du6oFSVUe2Dzdb/GUZ n5nD+KXnj3xkjvJpMqfereyaxZDW4xKQfWrQZ8AQ6YKcs07H7HzYEKxmUg9SKTgbj9e1 MgaK2OxayeX6jyz3ZBbz3I+GMYTxEOavf4Sh84ZQCWdgCB1la3pCLY+zfxSLQby3c87G XXlOFIFBJuGp4ihpOdGsxG4GWqYL79Nonw9C/5a2Lkn9D7tU3rDo+Ae2JWtGSOamjwbZ xQUw== X-Gm-Message-State: ALoCoQlMjGeSQn5PdH62vm9UgVJVQLi/tWq7Fb/XOBt2buKvCxFp+uakK1k6hs2+USEjNcwNiT5i X-Received: by 10.112.159.195 with SMTP id xe3mr30397603lbb.64.1425987275436; Tue, 10 Mar 2015 04:34:35 -0700 (PDT) Received: from tn-HP-4.semihalf.com (cardhu.semihalf.com. [213.17.239.108]) by mx.google.com with ESMTPSA id n12sm57206lbg.31.2015.03.10.04.34.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 10 Mar 2015 04:34:33 -0700 (PDT) From: Tomasz Nowicki To: bhelgaas@google.com, wangyijing@huawei.com, arnd@arndb.de, hanjun.guo@linaro.org, Liviu.Dudau@arm.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, rjw@rjwysocki.net, al.stone@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, Tomasz Nowicki Subject: [PATCH v3 1/9] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs. Date: Tue, 10 Mar 2015 12:35:12 +0100 Message-Id: <1425987320-15020-2-git-send-email-tomasz.nowicki@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425987320-15020-1-git-send-email-tomasz.nowicki@linaro.org> References: <1425987320-15020-1-git-send-email-tomasz.nowicki@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - fix typo - improve explanation - add reference to the related document Signed-off-by: Tomasz Nowicki --- arch/x86/include/asm/pci_x86.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index fa1195d..d024f4d 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -152,10 +152,13 @@ extern struct list_head pci_mmcfg_list; /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space - * on their northbrige except through the * %eax register. As such, you MUST - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config + * on their northbridge except through the * %eax register. As such, you MUST + * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_* * accessor functions. - * In fact just use pci_config_*, nothing else please. + * + * Please refer to the following doc: + * "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors", + * rev. 3.48, sec 2.11.1, "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) {