From patchwork Wed Mar 11 14:12:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 5985291 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 145889F399 for ; Wed, 11 Mar 2015 14:12:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3590420443 for ; Wed, 11 Mar 2015 14:12:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 63B852043C for ; Wed, 11 Mar 2015 14:12:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751724AbbCKOMs (ORCPT ); Wed, 11 Mar 2015 10:12:48 -0400 Received: from mail-la0-f49.google.com ([209.85.215.49]:38168 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751124AbbCKOMf (ORCPT ); Wed, 11 Mar 2015 10:12:35 -0400 Received: by labhs14 with SMTP id hs14so8564261lab.5 for ; Wed, 11 Mar 2015 07:12:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XubwWYOsv3Nxc7e+lrSYN1gukLOM4gdx/jBhbo4T9uw=; b=AyqHugPxks66PNRe1qUJpNWDfij1DR4I3XS7xplU78jiirrzgnqzXahRNXrKakQsXn kdGJY6FEkUnGhSUpHmzoT4PGyr3S75B2QEDcWlwRF5GYTNbvZepHId2Y/GuSC1kWngYR gGVqLKsU98ZsjltipYj5sp5tD0oCokQiltu6y+HdLfuFsDpC7MxPcWL9uuvmO/eprnm1 5wqjUCHUxgJgqM25ZK4D97pyl6YCGNzDYVRrOVbBQcNmi0yzYRjaFtIYRjiXCREA8hs9 3H0gUN8VzfO+88ahLHdfKMKDU33GIZH6ojfDz9h6ZtzJjIi/J4KWzwifo/56un7imieZ cE9w== X-Gm-Message-State: ALoCoQketWQexbQEZ9NdgZJLWDpdI5EWL4FRDiCigtQ7cy7Xq/u/T9rkq5CvHLbWYvPHGhDSYVAy X-Received: by 10.112.130.195 with SMTP id og3mr34314174lbb.112.1426083153901; Wed, 11 Mar 2015 07:12:33 -0700 (PDT) Received: from tn-HP-4.semihalf.com (cardhu.semihalf.com. [213.17.239.108]) by mx.google.com with ESMTPSA id x4sm746600lba.22.2015.03.11.07.12.31 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Mar 2015 07:12:33 -0700 (PDT) From: Tomasz Nowicki To: bhelgaas@google.com, wangyijing@huawei.com, arnd@arndb.de, hanjun.guo@linaro.org, Liviu.Dudau@arm.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, rjw@rjwysocki.net, al.stone@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, Tomasz Nowicki Subject: [PATCH v4 1/9] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs. Date: Wed, 11 Mar 2015 15:12:41 +0100 Message-Id: <1426083169-8698-2-git-send-email-tomasz.nowicki@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426083169-8698-1-git-send-email-tomasz.nowicki@linaro.org> References: <1426083169-8698-1-git-send-email-tomasz.nowicki@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - fix typo - improve explanation - add reference to the related document Signed-off-by: Tomasz Nowicki --- arch/x86/include/asm/pci_x86.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index fa1195d..d024f4d 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -152,10 +152,13 @@ extern struct list_head pci_mmcfg_list; /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space - * on their northbrige except through the * %eax register. As such, you MUST - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config + * on their northbridge except through the * %eax register. As such, you MUST + * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_* * accessor functions. - * In fact just use pci_config_*, nothing else please. + * + * Please refer to the following doc: + * "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors", + * rev. 3.48, sec 2.11.1, "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) {