From patchwork Wed Apr 15 06:04:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Wang X-Patchwork-Id: 6218821 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BCA239F398 for ; Wed, 15 Apr 2015 06:04:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4CA2620376 for ; Wed, 15 Apr 2015 06:04:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5C6322035E for ; Wed, 15 Apr 2015 06:04:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933218AbbDOGEL (ORCPT ); Wed, 15 Apr 2015 02:04:11 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:28615 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932772AbbDOGEK (ORCPT ); Wed, 15 Apr 2015 02:04:10 -0400 Received: from 172.24.2.119 (EHLO szxeml428-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CMD23198; Wed, 15 Apr 2015 14:04:03 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.158.1; Wed, 15 Apr 2015 14:03:53 +0800 From: Zhou Wang To: Bjorn Helgaas , Mohit Kumar , Jingoo Han , Arnd Bergmann , Liviu Dudau CC: , , , , , , , , , , Zhou Wang Subject: [RFC PATCH 3/3] Documentation: devicetree: Add hisilicon PCIe host binding Date: Wed, 15 Apr 2015 14:04:03 +0800 Message-ID: <1429077843-184462-4-git-send-email-wangzhou1@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1429077843-184462-1-git-send-email-wangzhou1@hisilicon.com> References: <1429077843-184462-1-git-send-email-wangzhou1@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Zhou Wang --- .../devicetree/bindings/pci/hisilicon-pcie.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt new file mode 100644 index 0000000..c24578d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -0,0 +1,46 @@ +Hisilicon PCIe host bridge DT description + +Hisilicon PCIe host controller is based on Designware PCI core. +It shares common functions with PCIe Designware core driver and inherits +common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties: +- compatible: Should contain "hisilicon,hip05-pcie". +- reg: Should contain rc_dbi, subctrl, config registers location and length. +- reg-names: Must include the following entries: + "rc_dbi": controller configuration registers; + "subctrl": whole PCIe hosts configuration registers; + "config": PCIe configuration space registers. +- msi-parent: Should be its_pcie which is an its receiving MSI interrupts. +- port-id: Should be 0, 1, 2 or 3. + +Optional properties: +- status: Either "ok" or "disabled". +- dma-coherent: Present if dma operations are coherent. + +Example: + pcie@0xb0080000 { + compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; + reg = <0 0xb0080000 0 0x10000>, <0 0xb0000000 0 0x10000>, + <0x220 0x00000000 0 0x1000>; + reg-names = "rc_dbi", "subctrl", "config"; + bus-range = <0 15>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x82000000 0 0xb4100000 0x220 0x00100000 0 0x00f00000>; + num-lanes = <8>; + port-id = <1>; + #interrupts-cells = <1>; + interrupts-map-mask = <0xf800 0 0 7>; + interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10 + 0x0 0 0 2 &mbigen_pcie 2 11 + 0x0 0 0 3 &mbigen_pcie 3 12 + 0x0 0 0 4 &mbigen_pcie 4 13>; + status = "ok"; + };