From patchwork Tue May 26 12:49:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 6479581 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D5DC19F38C for ; Tue, 26 May 2015 12:52:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F2AB0205EC for ; Tue, 26 May 2015 12:52:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9A69820614 for ; Tue, 26 May 2015 12:52:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752817AbbEZMw3 (ORCPT ); Tue, 26 May 2015 08:52:29 -0400 Received: from mail-pd0-f177.google.com ([209.85.192.177]:35696 "EHLO mail-pd0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752768AbbEZMw3 (ORCPT ); Tue, 26 May 2015 08:52:29 -0400 Received: by pdea3 with SMTP id a3so90220881pde.2 for ; Tue, 26 May 2015 05:50:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OZ8nvePW/nDcEZRc/slj+aNZCG6KJ0GAj9XYuCssMzo=; b=IxSWEE4n7Vwt2g0qybmLkoD+rk6cxFirqzYJC0CzPrYty7LTypxw8rv9mnxLFu0hZG duTcNoTOI6jhO5rIJ8UExTowoKecaIhTFEYYC1iZL5nRrZI/8rBurqHpt7xRReHtsLRq vqS8PJj2mk7DBTKAMcKLP9E4RsNWqreJkVW2toX21i7zXz08xdL3e6qOIkoABWUJnk36 +/IzDGErrgjKXxs1YaDBWQPCkbTRZ6NBOakHrSCN9pjBS8hvx1sR0ztDHd+Dx69OaSGg EzRKiYwPUtWO3xfUq4I317EThv1fWGiQJDdV9O2My0NWa5nlbi3hv3BSeBmkqEGdslo7 gRsg== X-Gm-Message-State: ALoCoQnvgkx4AT3Atx6goIOh3L/PznG0T/ylhOgHyr2zDxj/Y3rGgqsGnfFbVWN66sqWM/Gax4B7 X-Received: by 10.70.29.164 with SMTP id l4mr48515657pdh.32.1432644615402; Tue, 26 May 2015 05:50:15 -0700 (PDT) Received: from localhost ([180.150.153.56]) by mx.google.com with ESMTPSA id dv9sm12861625pac.4.2015.05.26.05.50.13 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 26 May 2015 05:50:14 -0700 (PDT) From: Hanjun Guo To: Bjorn Helgaas , Arnd Bergmann , Catalin Marinas , Will Deacon , "Rafael J. Wysocki" Cc: Jiang Liu , Liviu Dudau , Thomas Gleixner , Yijing Wang , Lorenzo Pieralisi , Tomasz Nowicki , Suravee Suthikulpanit , Mark Salter , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org, Hanjun Guo Subject: [PATCH 02/11] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs. Date: Tue, 26 May 2015 20:49:15 +0800 Message-Id: <1432644564-24746-3-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432644564-24746-1-git-send-email-hanjun.guo@linaro.org> References: <1432644564-24746-1-git-send-email-hanjun.guo@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Nowicki - fix typo - improve explanation - add reference to the related document Signed-off-by: Tomasz Nowicki Signed-off-by: Hanjun Guo Tested-by: Suravee Suthikulpanit --- arch/x86/include/asm/pci_x86.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 164e3f8..eddf8f0 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -154,10 +154,13 @@ extern struct list_head pci_mmcfg_list; /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space - * on their northbrige except through the * %eax register. As such, you MUST - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config + * on their northbridge except through the * %eax register. As such, you MUST + * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_* * accessor functions. - * In fact just use pci_config_*, nothing else please. + * + * Please refer to the following doc: + * "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors", + * rev. 3.48, sec 2.11.1, "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) {