From patchwork Tue Jul 14 22:47:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 6789551 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9AA0E9F380 for ; Tue, 14 Jul 2015 22:49:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9BF4F2073F for ; Tue, 14 Jul 2015 22:49:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 89E1C2073C for ; Tue, 14 Jul 2015 22:49:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753277AbbGNWsM (ORCPT ); Tue, 14 Jul 2015 18:48:12 -0400 Received: from userp1040.oracle.com ([156.151.31.81]:35358 "EHLO userp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753046AbbGNWsL (ORCPT ); Tue, 14 Jul 2015 18:48:11 -0400 Received: from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234]) by userp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id t6EMlpTa012616 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 14 Jul 2015 22:47:52 GMT Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserv0022.oracle.com (8.13.8/8.13.8) with ESMTP id t6EMlpse021743 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL); Tue, 14 Jul 2015 22:47:51 GMT Received: from abhmp0014.oracle.com (abhmp0014.oracle.com [141.146.116.20]) by aserv0122.oracle.com (8.13.8/8.13.8) with ESMTP id t6EMlpRP020074; Tue, 14 Jul 2015 22:47:51 GMT Received: from linux-siqj.site.us.oracle.com (/10.132.127.48) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Tue, 14 Jul 2015 15:47:51 -0700 From: Yinghai Lu To: Bjorn Helgaas , David Miller , Benjamin Herrenschmidt , Wei Yang , TJ , Yijing Wang Cc: Andrew Morton , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yinghai Lu Subject: [PATCH v2 37/49] PCI: Restore pref mmio allocation logic for hostbridge without mmio64 Date: Tue, 14 Jul 2015 15:47:08 -0700 Message-Id: <1436914040-13206-38-git-send-email-yinghai@kernel.org> X-Mailer: git-send-email 1.8.4.5 In-Reply-To: <1436914040-13206-1-git-send-email-yinghai@kernel.org> References: <1436914040-13206-1-git-send-email-yinghai@kernel.org> X-Source-IP: aserv0022.oracle.com [141.146.126.234] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From 5b2854155 (PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources), we change the logic for pref mmio allocation: When bridge pref support mmio64, we will only put children pref that support mmio64 into it, and will put children pref mmio32 into bridge's non-pref mmio32. That could leave bridge pref bar not used when that pref bar is mmio64, and children res only has mmio32. Also could have allocation failure when non-pref mmio32 is not big enough space for those children pref mmio32. That is not rational when the host bridge does not 64bit mmio above 4g at all. The patch restore to old logic: when hostbridge does not have has_mem64 so put children pref mmio64 and pref mmio32 all under bridges pref bars. Signed-off-by: Yinghai Lu --- drivers/pci/bus.c | 4 +++- drivers/pci/setup-bus.c | 13 +++++++++---- drivers/pci/setup-res.c | 9 ++++++--- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 6fbd3f2..b043bdf 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -202,8 +202,10 @@ int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res, { #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT int rc; + unsigned long mmio64 = pci_find_host_bridge(bus)->has_mem64 ? + IORESOURCE_MEM_64 : 0; - if (res->flags & IORESOURCE_MEM_64) { + if (res->flags & mmio64) { rc = pci_bus_alloc_from_region(bus, res, size, align, min, type_mask, alignf, alignf_data, &pci_high); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 37d5a48..f5b07d8 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1876,7 +1876,8 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; mask = IORESOURCE_MEM; prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (b_res[2].flags & IORESOURCE_MEM_64) { + if ((b_res[2].flags & IORESOURCE_MEM_64) && + pci_find_host_bridge(bus)->has_mem64) { prefmask |= IORESOURCE_MEM_64; ret = pbus_size_mem(bus, prefmask, prefmask, prefmask, prefmask, @@ -2032,17 +2033,21 @@ static void pci_bridge_release_resources(struct pci_bus *bus, * io port. * 2. if there is non pref mmio assign fail, release bridge * nonpref mmio. - * 3. if there is 64bit pref mmio assign fail, and bridge pref + * 3. if there is pref mmio assign fail, and host bridge does + * have 64bit mmio, release bridge pref mmio. + * 4. if there is 64bit pref mmio assign fail, and bridge pref * is 64bit, release bridge pref mmio. - * 4. if there is pref mmio assign fail, and bridge pref is + * 5. if there is pref mmio assign fail, and bridge pref is * 32bit mmio, release bridge pref mmio - * 5. if there is pref mmio assign fail, and bridge pref is not + * 6. if there is pref mmio assign fail, and bridge pref is not * assigned, release bridge nonpref mmio. */ if (type & IORESOURCE_IO) idx = 0; else if (!(type & IORESOURCE_PREFETCH)) idx = 1; + else if (!pci_find_host_bridge(bus)->has_mem64) + idx = 2; else if ((type & IORESOURCE_MEM_64) && (b_res[2].flags & IORESOURCE_MEM_64)) idx = 2; diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index b19aa5b..26aedde 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -205,6 +205,8 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, struct resource *res = dev->resource + resno; resource_size_t min; int ret; + unsigned long mmio64 = pci_find_host_bridge(bus)->has_mem64 ? + IORESOURCE_MEM_64 : 0; min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; @@ -216,7 +218,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, * things differently than they were sized, not everything will fit. */ ret = pci_bus_alloc_resource(bus, res, size, align, min, - IORESOURCE_PREFETCH | IORESOURCE_MEM_64, + IORESOURCE_PREFETCH | mmio64, pcibios_align_resource, dev); if (ret == 0) return 0; @@ -225,7 +227,8 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, * If the prefetchable window is only 32 bits wide, we can put * 64-bit prefetchable resources in it. */ - if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == + if (mmio64 && + (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { ret = pci_bus_alloc_resource(bus, res, size, align, min, IORESOURCE_PREFETCH, @@ -240,7 +243,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, * non-prefetchable, the first call already tried the only possibility * so we don't need to try again. */ - if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) + if (res->flags & (IORESOURCE_PREFETCH | mmio64)) ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, pcibios_align_resource, dev);