From patchwork Wed Aug 26 11:14:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 7075891 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A9E429F344 for ; Wed, 26 Aug 2015 11:08:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D9E5F2076E for ; Wed, 26 Aug 2015 11:08:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 77EDC20640 for ; Wed, 26 Aug 2015 11:08:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756780AbbHZLIC (ORCPT ); Wed, 26 Aug 2015 07:08:02 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:63781 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756402AbbHZLIB (ORCPT ); Wed, 26 Aug 2015 07:08:01 -0400 Received: from 172.24.1.50 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.50]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CRG71274; Wed, 26 Aug 2015 19:07:56 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Wed, 26 Aug 2015 19:07:48 +0800 From: Gabriele Paoloni To: , , CC: , , , , , , gabriele paoloni Subject: [PATCH] PCI: Designware: Move num-lanes property read to dw_pcie_setup_rc Date: Wed, 26 Aug 2015 19:14:16 +0800 Message-ID: <1440587656-84224-1-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: gabriele paoloni Currently num-lanes is read in dw_pcie_host_init(). for A SoC that performs the link-up operation in UEFI num-lanes is not needed in the DTS but it has to be specified to any value; otherwise dw_pcie_host_init will fail. This patch moves the num-lanes property read in dw_pcie_setup_rc() as num-lanes is only used there and, if the link is already up, the PCIe controller driver can decide either to leave host_init NULL or to return straightforward without proceeding to call dw_pcie_setup_rc(). Signed-off-by: Gabriele Paoloni --- drivers/pci/host/pcie-designware.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 69486be..7d707b7 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -483,11 +483,6 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { - dev_err(pp->dev, "Failed to parse the number of lanes\n"); - return -EINVAL; - } - if (IS_ENABLED(CONFIG_PCI_MSI)) { if (!pp->ops->msi_host_init) { pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, @@ -742,7 +737,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 val; u32 membase; u32 memlimit; + struct device_node *np = pp->dev->of_node; + if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { + dev_err(pp->dev, "Failed to parse the number of lanes\n"); + return; + } /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK;